Research Output

¿MOS enhanced differential current-switch threshold logic gates

Li, KC., Padure, MD. & Cotofana, SD., 2005, Proceedings of ProRISC 2005, 16th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 530-535 6 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

(When) will CMPs hit the power wall?

Meenderinck, CH. & Juurlink, B., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: STW, p. 156-159 4 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

2.5n-Step sorting on nxn meshes in the presence of 0(Vn) worst-case faults

Varvarigos, EA., Parhami, B. & Yeh, CH., 1999, IPPS/SPDP 1999. Los Alamitos: IEEE, p. 436-440 5 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

2007 International conference on field programmable logic and applications

Bertels, K., Najjar, W., van Genderen, AJ. & Vassiliadis, S., 2007, Piscataway: IEEE Society. 811 p.

Research output: Book/ReportBookProfessional

2-output spin wave programmable logic gate

Mahmoud, A., Vanderveken, F., Adelmann, C., Ciubotaru, F., Cotofana, S. & Hamdioui, S., 2020, 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI): Proceedings. O'Conner, L. (ed.). Piscataway: IEEE, p. 60-65 6 p. 9155012

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Open Access
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4 Downloads (Pure)

3D/ 2.5D stacked IC cost modeling and test flow selection

Hamdioui, S., 2014, p. 1-1. 1 p.

Research output: Contribution to conferenceAbstractScientific

Open Access

3D compaction: a novel blocking-aware algorithm for online hardware task scheduling and placement on 2D partially reconfigurable devices

Thomas, TM., Lu, Y., Bertels, K. & Gaydadjiev, GN., 2010, 6th Intl. symp. ARC 2010. Sirisuk, P., Morgan, F., El-Ghazawi, T. & Amano, H. (eds.). Berlijn: Springer, p. 194-206 13 p. (Lecture Notes in Computer Science; vol. 5992).

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

13 Citations (Scopus)

3D-COSTAR: a cost model for 3D stacked ICs

Taouil, M., Hamdioui, S., Marinissen, EJ. & Bhawmik, S., 2012, Proceedings Third IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits. Zorian, Y., Marijnissen, E. & Hamdioui, S. (eds.). Los Alamitos, CA, USA: IEEE, p. 1-6 6 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

3D graphics benchmarks for low-power architectures

Antochi, I., Juurlink, BHH., Vassiliadis, S. & Liuha, P., 2003, Proceedings of ProRISC 2003. s.n. (ed.). Utrecht: STW, p. 18-22 5 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

3D graphics tile-based systolic scan-conversion

Crisu, D., Vassiliadis, S., Cotofana, SD. & Liuha, P., 2004, Signals, Systems and Computers, 2004. Conference Record of the Thirty-Eighth Asilomar Conference on. Matthews, MB. (ed.). Piscataway: IEEE Society, p. 517-521 5 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Open Access

3D stacked wide-operand adders: A case study

Voicu, GR., Lefter, M., Enachescu, M. & Cotofana, SD., 2013, Proceedings 2013 IEEE 24th International Conference on Application-specific Systems, Architectures and Processors. El-Ghawazi, T. & Smith et al, M. (eds.). Los Alamitos, CA, USA: IEEE, p. 133-141 9 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Open Access
2 Citations (Scopus)

3D-TV rendering on a multiprocessor system on a chip

Li, X., van Eijndhoven, JTJ. & Juurlink, BHH., 2004, Proceedings of Pro-RISC 2004. Utrecht: Technology Foundation STW, p. 271-282 12 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

3-Tier reconfiguration model for FPGAs using hardwired network on chip

Wahlah, MA. & Goossens, KGW., 2009, 2009 intl. conf. on field-programmable technology. Bergmann, N., Diessel, O. & Shannon, L. (eds.). Piscataway: IEEE Society, p. 504-509 6 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

4 Citations (Scopus)

64-bit floating-point FPGA matrix multiplication

Dou, Y., Vassiliadis, S., Kuzmanov, GK. & Gaydadjiev, GN., 2005, Proceedings of the 2005 ACM/SIGDA 13th international symposium on field-programmable gate arrays (FPGA '05). s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 86-95 10 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

141 Citations (Scopus)

7/3 and 7/2 Counters implemented in single electron technology

Lageweg, CR., Cotofana, SD. & Vassiliadis, S., 2002, Proceedings of ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 344-350 7 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

A 2×13-bit all-digital I/Q RF-DAC in 65-nm CMOS

Alavi, SM., Voicu, GR., Staszewski, RB., de Vreede, LCN. & Long, JR., 2013, Digest of Papers - 2013 IEEE Radio Frequency Integrated Circuits Symposium. Hancock, TM. (ed.). Piscataway, NJ, USA: IEEE Society, p. 167-170 4 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Open Access
15 Citations (Scopus)

A 2D adressing mode for multimedia applications

Kuzmanov, GK., Vassiliadis, S. & van Eijndhoven, JTJ., 2002, Embedded processor design challenges: Systems, Architectures, Modeling, and Simulation - SAMOS. Deprettere, EF., Teich, J. & Vassiliadis, S. (eds.). Berlin: Springer, p. 291-307 16 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

A 3D-audio reconfigurable processor

Theodoropoulos, D., Kuzmanov, GK. & Gaydadjiev, GN., 2010, Eighteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 107-110 4 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

6 Citations (Scopus)

A 3D stacked high performance scalable architecture for 3D fourier transform

Voicu, GR., Enachescu, M. & Cotofana, SD., 2012, 30th IEEE international conference on computer design. s.n. (ed.). New York: IEEE Society, p. 1-2 2 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

A cache architecture for counting bloom filters

Ahmadi, M. & Wong, S., 2007, 15th International conference on networks. s.n. (ed.). Piscataway: IEEE Society, p. 218-223 6 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

14 Citations (Scopus)

A Cache Architecture for Counting Bloom Filters: Theory and Application

Ahmadi, M. & Wong, JSSM., 2011, In : Journal of Electrical and Computer Engineering. 2011, p. 1-10 10 p.

Research output: Contribution to journalArticleScientificpeer-review

Open Access
1 Citation (Scopus)

A cache-based hardware accelerator for memory data movements

Campos Soares Borrego, F., 2008, 160 p.

Research output: ThesisDissertation (TU Delft)

A case for hardware task management support for the StarSS programming

Meenderinck, CH. & Juurlink, BHH., 2010, 13th Euromicro conf. on digital systems design, architectures, methods and tools. s.n. (ed.). Piscataway: IEEE Society, p. 347-354 8 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

11 Citations (Scopus)

Accelarating color space conversion using extended subwords and the matrix register file

Shahbahrami, A., Juurlink, B. & Vassiliadis, S., 2006, Eighth IEEE international Symposium on multimedia. Piscataway: IEEE Society, p. 37-44 8 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

9 Citations (Scopus)

Accelerating a geometrical approximated PCA algorithm using AVX2 and CUDA

Machidon, A. L., Machidon, O. M., Ciobanu, C. B. & Ogrutan, P. L., 2020, In : Remote Sensing. 12, 12, p. 1-29 29 p., 1918.

Research output: Contribution to journalArticleScientificpeer-review

Open Access
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1 Downloads (Pure)

Accelerating complex brain-model simulations on GPU platforms

Nguyen, HAD., Al-Ars, Z., Smaragdos, G. & Strydis, C., 2015, Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition. Nebel, W. (ed.). Piscataway, NJ, USA: IEEE Society, p. 974-979 6 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

11 Citations (Scopus)

Accelerating DNA Variant Calling Algorithms on High Performance Computing Systems

Ren, S., 2018, 83 p.

Research output: ThesisDissertation (TU Delft)

Open Access
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49 Downloads (Pure)

Accelerating the secure remote password protocol using reconfigurable hardware

Groen, PT., Hämäläinen, P., Juurlink, BHH. & Hämäläinen, T., 2004, 2004 Computing Frontier Conference. New York: Association for Computing Machinery (ACM), p. 471-480 10 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

1 Citation (Scopus)

Acceleration of Bioinformatics Sequence Alignment - A Hardware Perspective

Hasan, L., 2011, Germany: LAP LAMBERT Academic Publishing. 132 p.

Research output: Book/ReportBookScientific

Acceleration of biological sequence alignment using recursive variable expansion

Nawaz, Z., Shabbir, M., Al-Ars, Z. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 233-237 5 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Acceleration of Smith-Waterman using recursive variable expansion

Nawaz, Z., Shabbir, M., Al-Ars, Z. & Bertels, KLM., 2008, 11th Euromicro Conference on Digital System Design, Architectures, Methods and tools. Fanucci, L. (ed.). s.n., p. 915-922 8 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

7 Citations (Scopus)

Accurate profiling and acceleration evaluation of the Smith-Waterman algorithm using the Molen platform

Hasan, L. & Al-Ars, Z., 2008, IADIS International Conference Applied Computing 2008. Nuno Guimaraes, P. I. (ed.). Portugal: IADIS Press, p. 188-194 7 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Achieving fanout capabilities in single electron encoded logic networks

Lageweg, C., Cotofana, SD. & Vassiliadis, S., 2001, Proceedings. Vol. 2. Piscataway: IEEE Society, p. 1383-1386 4 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

11 Citations (Scopus)

A chip multiprocessor accelerator for video decoding

Meenderinck, CH. & Juurlink, B., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 63-71 9 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

A clustering method for the identification of convex disconnected multiple output instructions

Galuzzi, C., Theodoropoulos, D. & Bertels, K., 2008, IC - SAMOS 2008. W. Najjar, H. B. (ed.). Piscataway: IEEE Society, p. 65-73 9 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

1 Citation (Scopus)

A CMOS flip-flop featuring embedded threshold logic functions

Padure, MD., Cotofana, SD. & Vassiliadis, S., 2002, Proceedings ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 388-392 5 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

A CMOS semi-custom chip for mixed signal designs

van Genderen, AJ., Cotofana, SD., de Graaf, G., Kaichouhi, A., Liedorp, J., Nouta, R., Pertijs, MAP. & Verhoeven, CJM., 2004, Proceedings of Pro-RISC 2004. Utrecht: Technology Foundation STW, p. 191-196 6 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

A communication aware online task scheduling algorithm for FPGA-based partially reconfigurable systems

Lu, Y., Thomas, TM., Bertels, K. & Gaydadjiev, GN., 2010, 18th IEEE Field-programmable custom computing machines. Sass, R. & Tessier, R. (eds.). Los Alamitos, CA: IEEE Society, p. 65-68 4 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

15 Citations (Scopus)

A Compact Low-Voltage True Random Number Generator Based on Inkjet Printing Technology

Erozan, A. T., Wang, G. Y., Bishnoi, R., Aghassi-Hagmann, J. & Tahoori, M. B., 2020, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 28, 6, p. 1485-1495 11 p.

Research output: Contribution to journalArticleScientificpeer-review

A comparison between processor architectures for multimedia applications

Shahbahrami, A., Juurlink, BHH. & Vassiliadis, S., 2004, Proceedings of Pro-RISC 2004. Utrecht: Technology Foundation STW, p. 1-15 15 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

A Comparison of Seed-and-Extend Techniques in Modern DNA Read Alignment Algorithms

Ahmed, N., Bertels, K. & Al-Ars, Z., Dec 2016, 2016 IEEE International Conference on Bioinformatics and Biomedicine (BIBM). Tian, T., Jiang, Q., Liu, Y., Burrage, K., Song, J., Wang, Y., Hu, X., Morishita, S., Zhu, Q. & Wang, G. (eds.). Piscataway, NJ: IEEE, p. 1421-1428 8 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

File
8 Citations (Scopus)
206 Downloads (Pure)

A comparison of two SIMD implementations of the 2D discrete wavelet transform

Shahbahrami, A. & Juurlink, B., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: STW, p. 169-177 9 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

A composable, energy-managed, realtimeMPSOC platform

Goossens, KGW., Molnos, AM., Ambrose, JA., Nelson, AT., Stefan, RA. & Cotofana, SD., 2010, 12th Intl. optimization electrical and electronic equipment. s.n. (ed.). s.l.: IEEE Society, p. 870-876 7 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

A Computation-In-Memory Accelerator Based on Resistive Devices

Du Nguyen, H. A., Yu, J., Abu Lebdeh, M., Taouil, M. & Hamdioui, S., 2019, Proceedings of the International Symposium on Memory Systems. New York: Association for Computing Machinery (ACM), p. 19-32 14 p. (ICPS: ACM International Conference Proceeding Series).

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

2 Downloads (Pure)

A control microarchitecture for fault-tolerant quantum computing

Fu, X., Lao, L., Bertels, K. & Almudever, C. G., 2019, In : Microprocessors and Microsystems. 70, p. 21-30 10 p.

Research output: Contribution to journalArticleScientificpeer-review

1 Citation (Scopus)

Active Resonator Reset in the Nonlinear Dispersive Regime of Circuit QED

Bultink, C. C., Rol, M. A., O'Brien, T. E., Fu, X., Dikken, B. C. S., Dickel, C., Vermeulen, R. F. L., De Sterke, J. C., Bruno, A., Schouten, R. N. & DiCarlo, L., 13 Sep 2016, In : Physical Review Applied. 6, 3, p. 1-10 034008.

Research output: Contribution to journalArticleScientificpeer-review

Open Access
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38 Citations (Scopus)
29 Downloads (Pure)

Adapting communication for adaptable processors: a multi-axis reconfiguration approach

Santos, PC., Nazar, GL., Anjam, F. & Wong, JSSM., 2012, International conference on ReConFigurable computing and FPGAs. s.n. (ed.). s.l.: s.n., p. 1-6 6 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Adapting voltage ramp-up time for temperature noise reduction on memory-based PUFs

Monteiro OliveiraCortez, AM., van der Leest, V., Maes, R., Schrijen, GJ. & Hamdioui, S., 2013, IEEE International symposium on hardware-oriented security and trust. s.n. (ed.). Piscataway: IEEE Society, p. 35-40 6 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

21 Citations (Scopus)

Adaption to dynamic resource availability in ad hoc grids through a learning mechanism

Pourebrahimi, B. & Bertels, KLM., 2008, 2008 IEEE 11th Intl. Conf. on Computational Science and Engineering. s.n. (ed.). s.l.: s.n., p. 171-178 8 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

8 Citations (Scopus)

Adaptive, low-power architectures for embedded multimedia systems: with focus on H.264/AVC video codec

Nadeem, M., 2014, 136 p.

Research output: ThesisDissertation (TU Delft)