Research Output

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2012

Conclusion: multi-core processor architectures are here to stay.

Bertels, KLM., 2012, Hardware/Software co-design for heterogeneous multi-core platforms. Bertels, KLM. (ed.). Berlin, Germany: Springer, p. 229-231 234 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientific

Extensions of the hArtes tool chain

Meeuws, RJ., Ostadzadeh, SA., Nawaz, Z., Lu, Y., Thomas, TM., Sabeghi, M., Sima, VM. & Sigdel, K., 2012, Hardware/Software co-design for heterogeneous multi-core platforms. Bertels, KLM. (ed.). Berlin, Germany: Springer, p. 193-227 234 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientific

Introduction

Bertels, KLM., 2012, Hardware/Software co-design for heterogeneous multi-core platforms. Bertels, KLM. (ed.). Berlin, Germany: Springer, p. 1-8 234 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientific

The hArtesplatform

Kuzmanov, GK., Tripiccione, R., Marchiori, G. & Colacicco, I., 2012, Hardware/Software co-design for heterogeneous multi-core platforms. Bertels, KLM. (ed.). Berlin, Germany: Springer, p. 111-123 234 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientific

The hArtes tool chain

Bertels, KLM., Meeuws, RJ., Yankova, YD., Sima, VM. & Sigdel, K., 2012, Hardware/Software co-design for heterogeneous multi-core platforms. Bertels, KLM. (ed.). Berlin, Germany: Springer, p. 9-109 234 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientific

2011

An Overview of Hardware-based Acceleration of Biological Sequence Alignment

Hasan, L. & Al-Ars, Z., 2011, Computational Biology and Applied Bioinformatics. Lopes, HS. & Cruz, LM. (eds.). Reijka, Croatia: Intech, p. 187-202 442 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientific

ERA-Embedded reconfigurable architectures

Wong, JSSM., Carro, L., Rutzig, M., Mota Mattos, D., Giorgi, R., Puzovic, N., Kaxiras, S., Cintra, M., Desoli, G., Gai, P., McKee, S. & Zaks, A., 2011, Reconfigurable Computing - From FPGAs to Hardware/Software Codesign. Cardoso, JMP. & Hubner, M. (eds.). Berlin - Heidelberg: Springer, p. 239-260 290 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientific

Open Access
6 Citations (Scopus)

hArtes: Holistic Approach to Reconfigurable Real-Time Embedded Systems

Kuzmanov, GK., Sima, VM., Bertels, KLM., Coutinho, G., Luk, W., Marchiori, G., Tripiccione, R. & Ferrandi, F., 2011, Reconfigurable Computing - From FPGAs to Hardware/Software Codesign. Cardoso, JMP. & Hübner, M. (eds.). Berlin - Heidelberg: Springer, p. 91-116 290 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientific

Open Access

HIPEAC: upcoming challenges in reconfigurable computing

Sourdis, I. & Gaydadjiev, GN., 2011, Reconfigurable Computing - From FPGAs to Hardware/Software Codesign. Cardoso, JMP. & Hubner, M. (eds.). Berlin - Heidelberg: Springer, p. 35-52 293 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientific

Open Access

REFLECT: Rendering FPGAs to Multi-core Embedded Computing

Cardoso, JMP., Bertels, KLM., Kuzmanov, GK., Nane, R. & Sima, VM., 2011, Reconfigurable Computing - From FPGAs to Hardware/Software Codesign. Cardoso, JMP. & Hubner, M. (eds.). Berlin - Heidelberg: Springer, p. 261-291 291 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientific

Open Access
2010

The synchronization challenge

Bertozzi, D., Strano, A., Ludovici, D. & Pavlidis, V., 2010, Designing network-on-chip architectures in the nanoscale era. Flich, J. & Bertozzi, D. (eds.). s.l.: s.n., p. 176-233 57 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

Topology exploration

Gilabert, F., Ludovici, D., Engracia Gomez, M. & Bertozzi, D., 2010, Designing network-on-chip architectures in the nanoscale era. Flich, J. & Bertozzi, D. (eds.). s.l.: s.n., p. 90-133 43 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

2009

The Molen organisation and programming paradigm

Bertels, K., Beemster, M., Sima, VM., Panainte, E. & Schoorel, M., 2009, Dynamic system reconfiguration in heterogeneous platforms- the Morpheus approach. Voros, N., Rosti, A. & Hubner, M. (eds.). New York: Springer, p. 119-128 270 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientific

2008

Resource allocation in market-based grids using a history-based pricing mechanism

Pourebrahimi, B., Ostadzadeh, SA. & Bertels, KLM., 2008, Advances in computer and information sciences and engineering. Sobh, T. (ed.). s.l.: Springer, p. 97-100 590 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

3 Citations (Scopus)

Trade offs in the design of a router with guaranteed and best-effort services for networks on chip

Rijpkema, E., Goossens, KGW., Radulescu, A. & Dielissen, J., 2008, Design, Automation, and Test in Europe. Lauwereins, R. & Madsen, J. (eds.). Heidelberg: Springer, p. 125-139 515 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

2 Citations (Scopus)
2007

ADRES & DRESC: Architecture and compiler for coarse-grain reconfigurable processors

Mei, B., Berekovic, M. & Mignolet, J-Y., 2007, Fine- and coarse-grain reconfigurable computing. Vassiliadis, S, S. D. (ed.). Heidelberg: Springer, p. 255-298 378 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

A survey of coarse-grain reconfigurable architectures and CAD tools

Theodoridis, G., Soudris, D. & Vassiliadis, S., 2007, Fine- and coarse-grain reconfigurable computing. Vassiliadis, S, S. D. (ed.). Heidelberg: Springer, p. 89-152 378 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

A taxonomy of field-programmable custom computing machines

Sima, M., Vassiliadis, S. & Cotofana, SD., 2007, Fine- and coarse-grain reconfigurable computing. Vassiliadis, S, S. D. (ed.). Heidelberg: Springer, p. 299-378 378 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

Polymorphic instruction set computers

Kuzmanov, GK. & Vassiliadis, S., 2007, Fine- and coarse-grain reconfigurable computing. Vassiliadis, S, S. D. (ed.). Heidelberg: Springer, p. 217-254 378 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

Static cache partitioning robustness analysis for embedded on-chip multi-processors

Molnos, AM., Cotofana, SD., Heijligers, MJM. & van Eijndhoven, JTJ., 2007, Transactions on high-performance embedded architectures and compilers I. Bodin, F Stenström, P, OB. M. & McKee, S (eds.). Berlin: Springer, p. 279-297 360 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

Vectorized aes core for high-throughput secure environments

Pericas, M., Chaves, PC., Gaydadjiev, GN. & Vassiliadis, S., 2007, The future of computing. Gaydadjiev, G Bertels, K, C. S. & Genderen van, A Hamdioui, S, J. B. (eds.). Delft: Computer Engineering TUDelft, p. 91-100 143 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

2006

Evaluation methodology for single electron encoded threshold logic gates

Lageweg, CR. & Cotofana, SD., 2006, VLSI-SOC: From Systems to Chips. Glesner, M., Reis, R., Indrusiak, L., Mooney, V. & Eveking, H. (eds.). New York, USA: Springer, p. 263-280 18 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

4 Citations (Scopus)
2004

Automatic VHDL model generation of parameterized FIR filters

Walters III, EG., Glossner, CJ. & Schulte, MJ., 2004, Domain-specific processors. Bhattacharyya, SS., Deprettere, EF. & Teich, J. (eds.). New York: Marcel Dekker, p. 1-18 18 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

Future directions of programmable and reconfigurable embedded processors

Wong, JSSM., Vassiliadis, S. & Cotofana, SD., 2004, Domain-specific processors; Systems, architectures, modeling, and simulation. Bhattacharyya, SS., Deprettere, EF. & Teich, J. (eds.). New York: Marcel Dekker, p. 235-258 24 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

The Sandbridge sandblaster communications processor

Glossner, CJ., Hokenek, E. & Moudgill, M., 2004, Software defined radio; Baseband technologies for 3G handsets and basestations. Tuttlebee, WHW. (ed.). Chichester, England: John Wiley & Sons, p. 129-160 32 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

2003

Introduction

van de Goor, AJ., Jha, N. & Gupta, S., 2003, Testing of digital systems. Cambridge: Cambridge University Press, p. 1-25 25 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

Memory testing

van de Goor, AJ., Jha, N. & Gupta, S., 2003, Testing of digital systems. Cambridge: Cambridge University Press, p. 845-892 48 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

On the use of Pierson distributions for the performance prediction of parallel programs

Reijns, GL., van Gemund, AJC. & Gautama, H., 2003, Performance evaluation - stories and perspectives. Kotsis, G. (ed.). Wien: Österreichische Computer Gesellschaft, p. 365-379 15 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

2002

A 2D adressing mode for multimedia applications

Kuzmanov, GK., Vassiliadis, S. & van Eijndhoven, JTJ., 2002, Embedded processor design challenges: Systems, Architectures, Modeling, and Simulation - SAMOS. Deprettere, EF., Teich, J. & Vassiliadis, S. (eds.). Berlin: Springer, p. 291-307 16 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

A Java-enabled DSP

Glossner, CJ., Schulte, MJ. & Vassiliadis, S., 2002, Embedded processor design challenges: Systems, Architectures, Modeling, and Simulation - SAMOS. Deprettere, EF., Teich, J. & Vassiliadis, S. (eds.). Berlin: Springer, p. 307-327 19 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

3 Citations (Scopus)

A reconfigurable functional unit for TriMedia/CPU64

Sima, M., Cotofana, SD., Vassiliadis, S. & van Eijndhoven, JTJ., 2002, Embedded processor design challenges: Systems, Architectures, Modeling and Simulation - SAMOS. Deprettere, EF., Teich, J. & Vassiliads, S. (eds.). Berlin: Springer, p. 224-242 18 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

1 Citation (Scopus)

Microcoded reconfigurable embedded processors: current developments

Wong, JSSM., Vassiliadis, S. & Cotofana, SD., 2002, Embedded processor design challenges: Systems, Architectures, Modeling, and Simulation - SAMOS. Deprettere, EF., Teich, J. & Vassiliadis, S. (eds.). Berlin: Springer, p. 207-224 17 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

The Delft-Java engine

Glossner, CJ. & Vassiliadis, S., 2002, Java microarchitectures. Narayanan, V. & Wolckzo, MI. (eds.). Boston: Kluwer Academic Publishers, p. 105-123 17 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

2001

Facilitating automatic test pattern generators using test point insertion

Geuzebroek, MJ., van de Goor Ph D, AJ. & van Linden, JT., 2001, Global Semiconductor Manufacturing Technology. Business Briefing, p. 149-152

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientific

Local distributed agent matchmaking

Ogston, E. & Vassiliadis, S., 2001, Cooperative information systems. C Batini & ... [et Al] (eds.). Berlin: Springer, p. 67-79

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

7 Citations (Scopus)

The MOLEN þµ-coded processor

Vassiliadis, S., Wong, JSSM. & Cotofana, SD., 2001, Field-progammable logic and applications. G Goos & ... [et Al] (eds.). Berlin: Springer, p. 275-285

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

53 Citations (Scopus)
1999

Computer architectuur, implementatie en realisatie

Corporaal, H., 1999, ICT-zakboekje. TMA Bemelmans, PME Bra, D., M Looijen & G Oortmerssen, V. (eds.). Arnhem: Koninklijke PBNA, p. 569-663

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterProfessional

Network routing algorithms

Varvarigos, EA. & Yeh, CH., 1999, Wiley encyclopedia of electrical and electronics engineering. New York: Wiley, p. 218-226

Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientific

22 Citations (Scopus)