N. Cucu Laurenciu

Dr.

20122020

Research output per year

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Research Output

  • 14 Conference contribution
  • 6 Article
  • 1 Dissertation (TU Delft)
2020

A study of graphene nanoribbon-based gate performance robustness under temperature variations

Jiang, Y., Laurenciu, N. C., Wang, H. & Cotofana, S. D., 2020, 2020 IEEE 20th International Conference on Nanotechnology (IEEE-NANO): Proceedings. IEEE, p. 62-66 5 p. 9183694

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Open Access
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1 Downloads (Pure)

Graphene Nanoribbon-based Synapses with Versatile Plasticity

Wang, H., Cucu Laurenciu, N., Jiang, Y. & Cotofana, S. D., 30 Apr 2020, IEEE International Symposium on Nanoscale Architectures (NANOARCH).

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Open Access
File

Reliability Aware Design and Lifetime Management of Computing Platforms

Cucu Laurenciu, N. & Cotofana, S. D., 2020, In : IEEE Transactions on Emerging Topics in Computing. 8, 3, p. 602-615 14 p., 8093761.

Research output: Contribution to journalArticleScientificpeer-review

Ultra-Compact, Entirely Graphene-based Nonlinear Leaky Integrate-and-Fire Spiking Neuron

Wang, H., Cucu Laurenciu, N., Jiang, Y. & Cotofana, S. D., 2020, ISCAS 2020: IEEE International Symposium On Circuits & Systems.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Open Access
File
2019

Atomistic-level hysteresis-aware graphene structures electron transport model

Wang, H., Cucu Laurenciu, N., Jiang, Y. & Cotofana, S. D., 2019, 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers (IEEE), Vol. 2019-May. p. 1-5 5 p. 8702106

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Open Access
File
2 Citations (Scopus)
1 Downloads (Pure)

Graphene Nanoribbon Based Complementary Logic Gates and Circuits

Jiang, Y., Cucu Laurenciu, N., Wang, H. & Cotofana, S. D., 2019, In : IEEE Transactions on Nanotechnology. 18, p. 287-298 12 p., 8666174.

Research output: Contribution to journalArticleScientificpeer-review

Open Access
File
1 Citation (Scopus)
131 Downloads (Pure)

Non-Equilibrium Green Function-based Verilog-A Graphene Nanoribbon Model

Jiang, Y., Laurenciu, N. C. & Cotofana, S. D., 2019, 2018 IEEE 18th International Conference on Nanotechnology (IEEE-NANO). Quinn, A., Li, G., Li, W. & Mathewson, A. (eds.). Piscataway, NJ, USA: IEEE, p. 1-4 4 p. 8626396

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

On Basic Boolean Function Graphene Nanoribbon Conductance Mapping

Jiang, Y., Laurenciu, N. C. & Cotofana, S. D., 2019, In : IEEE Transactions on Circuits and Systems I: Regular Papers. 66, 5, p. 1948-1959 12 p., 8574057.

Research output: Contribution to journalArticleScientificpeer-review

Open Access
File
1 Citation (Scopus)
102 Downloads (Pure)
2018

Complementary arranged graphene nanoribbon-based boolean gates

Jiang, Y., Laurenciu, N. C. & Cotofana, S., 17 Jul 2018, Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2018. Cotofana, S. & Sirakoulis, G. C. (eds.). New York, NY, USA: Association for Computing Machinery (ACM), p. 51-57 7 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

4 Citations (Scopus)

On Carving Basic Boolean Functions on Graphene Nanoribbons Conduction Maps

Jiang, Y., Cucu Laurenciu, N. & Cotofana, S., 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS) : Proceedings. Piscataway, NY: IEEE, p. 1-5 5 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

8 Citations (Scopus)

On Effective Graphene Based Computing

Laurenciu, N. C. & Cotofana, S. D., 2018, 2018 41st International Semiconductor Conference, CAS 2018 - Proceedings. Dinescu, M. A., Dobrescu, D., Muller, A., Cristea, D., Dragoman, M., Muller, R., Ciurea, M. L., Neculoiu, D. & Brezeanu, G. (eds.). Piscataway, NJ, USA: Institute of Electrical and Electronics Engineers (IEEE), Vol. 2018-October. p. 51-58 8 p. 8539757

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

2017

Fast and accurate workload-level neural network based IC energy consumption estimation

Cucu Laurenciu, N. & Cotofana, S., 2017, SMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design. IEEE, p. 1-4 4 p. 7981598

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Haar-based interconnect coding for energy effective medium/long range data transport

Cucu Laurenciu, N. & Cotofana, S., 2017, Proceedings - 30th IEEE International System on Chip Conference, SOCC 2017. Alioto, M., Li, H., Becker, J., Schlichtmann, U. & Sridhar, R. (eds.). Piscataway, NJ: IEEE, p. 375-380 6 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Reliability Aware Computing Platforms Design and Lifetime Management

Cucu Laurenciu, N., 2017, 132 p.

Research output: ThesisDissertation (TU Delft)

Open Access
File
22 Downloads (Pure)
2016

Error Correction Code protected Data Processing Units

Cucu Laurenciu, N., Gupta, T., Savin, V. & Cotofana, S., 2016, 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). Zhao, W. & Moritz, C. A. (eds.). New York: Association for Computing Machinery (ACM), p. 37-42 6 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

4 Citations (Scopus)
2015

Low cost and energy, thermal noise driven, probability modulated random number generator

Cucu Laurenciu, N. & Cotofana, SD., 2015, Proceedings - 2015 IEEE International Symposium on Circuits and Systems. de Medeiras Silva, M. (ed.). Piscataway, NJ, USA: IEEE Society, p. 2724-2727 4 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Open Access
4 Citations (Scopus)
2014

Critical transistors nexus based circuit-level aging assessment and prediction

Cucu Laurenciu, N. & Cotofana, SD., 2014, In : Journal of Parallel and Distributed Computing. 74, 6, p. 2512-2520 9 p.

Research output: Contribution to journalArticleScientificpeer-review

Open Access
1 Citation (Scopus)
2013

A direct measurement scheme of amalgamated aging effects with novel on-chip sensor

Cucu Laurenciu, N. & Cotofana, SD., 2013, 21st IFIP/IEEE international conference on very large scale integration. s.n. (ed.). Piscataway: IEEE Society, p. 1-6 6 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

5 Citations (Scopus)

A nonlinear degradation path dependent end-of-life estimation framework from noisy observations

Cucu Laurenciu, N. & Cotofana, SD., 2013, In : Microelectronics Reliability. 53, 9-11, p. 1213-1217 5 p.

Research output: Contribution to journalArticleScientificpeer-review

Open Access
12 Citations (Scopus)
2012

A Markovian, variation-aware circuit-level aging model

Cucu Laurenciu, N. & Cotofana, SD., 2012, International symposium on nanoscale architectures. s.n. (ed.). New York: IEEE Society, p. 1-7 7 p.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

1 Citation (Scopus)

Context aware slope based transistor-level aging model

Cucu Laurenciu, N. & Cotofana, SD., 2012, In : Microelectronics Reliability. 52, 9-10, p. 1-6 6 p.

Research output: Contribution to journalArticleScientificpeer-review

3 Citations (Scopus)