TY - GEN
T1 - 2-output spin wave programmable logic gate
AU - Mahmoud, Abdulqader
AU - Vanderveken, Frederic
AU - Adelmann, Christoph
AU - Ciubotaru, Florin
AU - Cotofana, Sorin
AU - Hamdioui, Said
N1 - Accepted author manuscript
PY - 2020
Y1 - 2020
N2 - This paper presents a 2-output Spin-Wave Programmable Logic Gate structure able to simultaneously evaluate any pair of AND, NAND, OR, NOR, XOR, and XNOR Boolean functions. Our proposal provides the means for fanout achievement within the Spin Wave computation domain and energy and area savings as two different functions can be simultaneously evaluated on the same input data. We validate our proposal by means of Object Oriented Micromagnetic Framework (OOMMF) simulations and demonstrate that by phase and magnetization threshold output sensing {AND, OR, NAND, NOR} and {XOR and XNOR} functionalities can be achieved, respectively. To get inside into the potential practical implications of our approach we use the proposed gate to implement a 3-input Majority gate, which we evaluate and compare with state of the art equivalent implementations in terms of area, delay, and energy consumptions. Our estimations indicate that the proposed gate provides 33% and 16% energy and area reduction, respectively, when compared with spin-wave counterpart and 42% energy reduction while consuming 12x less area when compared to a 15 nm CMOS implementation.
AB - This paper presents a 2-output Spin-Wave Programmable Logic Gate structure able to simultaneously evaluate any pair of AND, NAND, OR, NOR, XOR, and XNOR Boolean functions. Our proposal provides the means for fanout achievement within the Spin Wave computation domain and energy and area savings as two different functions can be simultaneously evaluated on the same input data. We validate our proposal by means of Object Oriented Micromagnetic Framework (OOMMF) simulations and demonstrate that by phase and magnetization threshold output sensing {AND, OR, NAND, NOR} and {XOR and XNOR} functionalities can be achieved, respectively. To get inside into the potential practical implications of our approach we use the proposed gate to implement a 3-input Majority gate, which we evaluate and compare with state of the art equivalent implementations in terms of area, delay, and energy consumptions. Our estimations indicate that the proposed gate provides 33% and 16% energy and area reduction, respectively, when compared with spin-wave counterpart and 42% energy reduction while consuming 12x less area when compared to a 15 nm CMOS implementation.
KW - Energy Efficiency
KW - Fan-out
KW - Programmable Logic
KW - Spin-wave
KW - Spin-wave Computation Paradigm
UR - http://www.scopus.com/inward/record.url?scp=85090417769&partnerID=8YFLogxK
U2 - 10.1109/ISVLSI49217.2020.00021
DO - 10.1109/ISVLSI49217.2020.00021
M3 - Conference contribution
AN - SCOPUS:85090417769
SN - 978-1-7281-5776-4
T3 - 2020 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2020)
SP - 60
EP - 65
BT - 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
A2 - O'Conner, L.
PB - IEEE
CY - Piscataway
T2 - 19th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2020
Y2 - 6 July 2020 through 8 July 2020
ER -