200 MS/s ADC implemented in a FPGA employing TDCs

Harald Homulle, Francesco Regazzoni, Edoardo Charbon

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

    14 Citations (Scopus)

    Abstract

    Analog signals are used in many applications and systems, such as cyber physical systems, sensor networks and automotive applications. These are also applications where the use of FPGAs is continuously growing. To date, however there is no direct integration between FPGAs, which are digital, and the analog world (except for the newest generation of FPGAs). Currently, an external analog-to-digital converter (ADC) has to be added to the system, thus limiting its overall compactness and flexibility.
    To address this issue we propose a novel architecture implementing a high speed ADC in reconfigurable devices. The system exploits picosecond resolution time-to-digital converters (TDCs) to reach a conversion as fast as its clock speed. The resulting analog-through-time-to-digital converter (ATDC) can achieve a sampling rate of 200 MS/s with a 7 bit resolution for signals ranging from 0 to 2.5 V. Except for the external resistor needed for the analog reference ramp, the system is fully integrated inside the target FPGA. Moreover, our design can be easily scaled for multichannel ADCs, proving the suitability of reconfigurable devices for applications requiring a deep integration between analog and digital world.
    Original languageEnglish
    Title of host publicationProceedings of the 23rd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
    EditorsD. Chen
    Place of PublicationNew York
    PublisherACM/SIGDA
    Pages228-235
    Number of pages8
    ISBN (Print)978-1-4503-3315-3
    DOIs
    Publication statusPublished - 2015
    EventFPGA 2015, Monterey, USA - New york
    Duration: 22 Feb 201524 Feb 2015
    http://www.eecs.ucf.edu/isfpga/

    Conference

    ConferenceFPGA 2015, Monterey, USA
    Period22/02/1524/02/15
    Internet address

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