3-Tier reconfiguration model for FPGAs using hardwired network on chip

MA Wahlah, KGW Goossens

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

4 Citations (Scopus)
Original languageUndefined/Unknown
Title of host publication2009 intl. conf. on field-programmable technology
EditorsN Bergmann, O Diessel, L Shannon
Place of PublicationPiscataway
PublisherIEEE Society
Pages504-509
Number of pages6
ISBN (Print)978-1-4244-4376-5
Publication statusPublished - 2009
EventFPT 2009 - Piscataway
Duration: 9 Dec 200911 Dec 2009

Publication series

Name
PublisherIEEE

Conference

ConferenceFPT 2009
Period9/12/0911/12/09

Keywords

  • conference contrib. refereed
  • Conf.proc. > 3 pag

Cite this

Wahlah, MA., & Goossens, KGW. (2009). 3-Tier reconfiguration model for FPGAs using hardwired network on chip. In N. Bergmann, O. Diessel, & L. Shannon (Eds.), 2009 intl. conf. on field-programmable technology (pp. 504-509). IEEE Society.