TY - GEN
T1 - 3.1 A 120.9dB DR, -111.2dB THD+N Digital-Input Capacitively-Coupled Chopper Class-D Audio Amplifier
AU - Zhang, Huajun
AU - Berkhout, Marco
AU - Makinwa, Kofi A.A.
AU - Fan, Qinwen
N1 - Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.
PY - 2023
Y1 - 2023
N2 - Class-D amplifiers (CDAs) are widely used in audio applications where a high power efficiency is required. As most audio sources are digital nowadays, implementing digital-input CDAs results in higher levels of integration and lower cost. However, prior open-loop digital-input CDAs suffer from high jitter sensitivity and output-stage distortion. In [1], jitter sensitivity at small signal levels is mitigated using a buck-boost converter that adaptively lowers the supply at the expense of extra external components and reduced power efficiency. Prior closed-loop digital-input CDAs employing multi-bit current-steering [2] or resistive [3] DACs are less sensitive to jitter, but their DR is limited to about 115dB. DAC non-idealities and intermodulation distortion are also challenges, and prior works only achieved a peak textTHD+N of about -98textdB [2], [3]. This paper presents a digital-input CDA that achieves high DR by combining a low-noise capacitive DAC (CDAC) with dedicated techniques to mitigate DAC mismatch, lSI, and intermodulation distortion. A prototype implemented in a 0.18mum BCD process achieves 120.9dB DR and -111.2textdB peak textTHD+N. Furthermore, it can deliver 13W/23W at 10% THD into an 8Omega/4Omega load with a 90%/86% efficiency.
AB - Class-D amplifiers (CDAs) are widely used in audio applications where a high power efficiency is required. As most audio sources are digital nowadays, implementing digital-input CDAs results in higher levels of integration and lower cost. However, prior open-loop digital-input CDAs suffer from high jitter sensitivity and output-stage distortion. In [1], jitter sensitivity at small signal levels is mitigated using a buck-boost converter that adaptively lowers the supply at the expense of extra external components and reduced power efficiency. Prior closed-loop digital-input CDAs employing multi-bit current-steering [2] or resistive [3] DACs are less sensitive to jitter, but their DR is limited to about 115dB. DAC non-idealities and intermodulation distortion are also challenges, and prior works only achieved a peak textTHD+N of about -98textdB [2], [3]. This paper presents a digital-input CDA that achieves high DR by combining a low-noise capacitive DAC (CDAC) with dedicated techniques to mitigate DAC mismatch, lSI, and intermodulation distortion. A prototype implemented in a 0.18mum BCD process achieves 120.9dB DR and -111.2textdB peak textTHD+N. Furthermore, it can deliver 13W/23W at 10% THD into an 8Omega/4Omega load with a 90%/86% efficiency.
UR - http://www.scopus.com/inward/record.url?scp=85151658923&partnerID=8YFLogxK
U2 - 10.1109/ISSCC42615.2023.10067400
DO - 10.1109/ISSCC42615.2023.10067400
M3 - Conference contribution
AN - SCOPUS:85151658923
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 54
EP - 56
BT - 2023 IEEE International Solid-State Circuits Conference, ISSCC 2023
PB - Institute of Electrical and Electronics Engineers (IEEE)
T2 - 2023 IEEE International Solid-State Circuits Conference, ISSCC 2023
Y2 - 19 February 2023 through 23 February 2023
ER -