TY - GEN
T1 - 31.2 A 0.9V 28MHz Dual-RC Frequency Reference with 5pJ/Cycle and ±200 ppm Inaccuracy from -40°C to 85°C
AU - Choi, Woojun
AU - Angevare, J.
AU - Park, Injun
AU - Makinwa, Kofi A.A.
AU - Chae, Youngcheol
PY - 2021
Y1 - 2021
N2 - Wireless sensor nodes in battery-powered internet-of-things (loT)
applications require a stable on-chip frequency reference with low
energy (<10 pJ / cycle) and high frequency stability (below ±300ppm).
CMOS RC frequency references are promising due to their low-cost
integration and high energy efficiency [1] –[5]. Conventional RC
references, however, achieve only moderate accuracy (a few %) due to the
large temperature coefficient (TC) of on-chip resistors [3].
First-order TC compensation can be achieved by combining resistors with
complementary TCs [1], [2]. Although this is energy efficient (<6 pJ /
cycle), it only partially compensates for the resistors’ high-order
TCs, limiting the resulting accuracy to about ±500 ppm. Better accuracy (±100
ppm [4]) can be achieved by using the output of a digital temperature
sensor (TS) to perform a polynomial correction of the phase-shift (μp,T) of an RC filter (Fig. 31.2.1). Alternatively, the phase-shifts (μp. and μN) of two RC filters with complementary TCs can be linearized (Tp. and T
N
) and combined in the digital domain. Such dual-RC frequency references can also achieve good accuracy (±200 ppm [5]). However, both architectures employ an analog phase-domain ΔΣ modulator (Φ−ΔΣM) for each RC filter, which consumes significant energy (25pJ/cycle [4] and 107pJ/ cycle [5]) and area (0.3mm2[4]. and 1.65mm2[5]).
AB - Wireless sensor nodes in battery-powered internet-of-things (loT)
applications require a stable on-chip frequency reference with low
energy (<10 pJ / cycle) and high frequency stability (below ±300ppm).
CMOS RC frequency references are promising due to their low-cost
integration and high energy efficiency [1] –[5]. Conventional RC
references, however, achieve only moderate accuracy (a few %) due to the
large temperature coefficient (TC) of on-chip resistors [3].
First-order TC compensation can be achieved by combining resistors with
complementary TCs [1], [2]. Although this is energy efficient (<6 pJ /
cycle), it only partially compensates for the resistors’ high-order
TCs, limiting the resulting accuracy to about ±500 ppm. Better accuracy (±100
ppm [4]) can be achieved by using the output of a digital temperature
sensor (TS) to perform a polynomial correction of the phase-shift (μp,T) of an RC filter (Fig. 31.2.1). Alternatively, the phase-shifts (μp. and μN) of two RC filters with complementary TCs can be linearized (Tp. and T
N
) and combined in the digital domain. Such dual-RC frequency references can also achieve good accuracy (±200 ppm [5]). However, both architectures employ an analog phase-domain ΔΣ modulator (Φ−ΔΣM) for each RC filter, which consumes significant energy (25pJ/cycle [4] and 107pJ/ cycle [5]) and area (0.3mm2[4]. and 1.65mm2[5]).
UR - http://www.scopus.com/inward/record.url?scp=85102344408&partnerID=8YFLogxK
U2 - 10.1109/ISSCC42613.2021.9366021
DO - 10.1109/ISSCC42613.2021.9366021
M3 - Conference contribution
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 434
EP - 436
BT - 2021 IEEE International Solid-State Circuits Conference, ISSCC 2021 - Digest of Technical Papers
PB - Institute of Electrical and Electronics Engineers (IEEE)
T2 - 2021 IEEE International Solid-State Circuits Conference, ISSCC 2021
Y2 - 13 February 2021 through 22 February 2021
ER -