TY - GEN
T1 - 4-output Programmable Spin Wave Logic Gate
AU - Mahmoud, Abdulqader
AU - Vanderveken, Frederic
AU - Adelmann, Christoph
AU - Ciubotaru, Florin
AU - Hamdioui, Said
AU - Cotofana, Sorin
PY - 2020
Y1 - 2020
N2 - To bring Spin Wave (SW) based computing paradigm into practice and develop ultra low power Magnonic circuits and computation platforms, one needs basic logic gates that operate and can be cascaded within the SW domain without requiring back and forth conversion between the SW and voltage domains. To achieve this, SW gates have to possess intrinsic fanout capabilities, be input-output data representation coherent, and reconfigurable. In this paper, we address the first and the last requirements and propose a novel 4-output programmable SW logic gate. First, we introduce the gate structure and demonstrate that, by adjusting the gate output detection method, it can parallelly evaluate any 4-element subset of the 2-input Boolean function set {(N)AND, (N)OR, and X(N)OR}. Furthermore, we adjust the structure such that all its 4 outputs produce SWs with the same energy and demonstrate that it can evaluate Boolean function sets while providing fanout capabilities ranging from 1 to 4. We validate our approach by instantiating and simulating different gate configurations such as 4-output AND/OR, 4-output XOR/XNOR, output energy balanced 4-output AND/OR, and output energy balanced 4-output XOR/XNOR by means of Object Oriented Micromagnetic Framework (OOMMF) simulations. Finally, we evaluate the performance of our proposal in terms of delay and energy consumption and compare it against existing state-of-the-art SW and 16 nm CMOS counterparts. The results indicate that for the same functionality, our approach provides 3× and 16× energy reduction, when compared with conventional SW and 16 nm CMOS implementations, respectively.
AB - To bring Spin Wave (SW) based computing paradigm into practice and develop ultra low power Magnonic circuits and computation platforms, one needs basic logic gates that operate and can be cascaded within the SW domain without requiring back and forth conversion between the SW and voltage domains. To achieve this, SW gates have to possess intrinsic fanout capabilities, be input-output data representation coherent, and reconfigurable. In this paper, we address the first and the last requirements and propose a novel 4-output programmable SW logic gate. First, we introduce the gate structure and demonstrate that, by adjusting the gate output detection method, it can parallelly evaluate any 4-element subset of the 2-input Boolean function set {(N)AND, (N)OR, and X(N)OR}. Furthermore, we adjust the structure such that all its 4 outputs produce SWs with the same energy and demonstrate that it can evaluate Boolean function sets while providing fanout capabilities ranging from 1 to 4. We validate our approach by instantiating and simulating different gate configurations such as 4-output AND/OR, 4-output XOR/XNOR, output energy balanced 4-output AND/OR, and output energy balanced 4-output XOR/XNOR by means of Object Oriented Micromagnetic Framework (OOMMF) simulations. Finally, we evaluate the performance of our proposal in terms of delay and energy consumption and compare it against existing state-of-the-art SW and 16 nm CMOS counterparts. The results indicate that for the same functionality, our approach provides 3× and 16× energy reduction, when compared with conventional SW and 16 nm CMOS implementations, respectively.
KW - Energy
KW - Programmable Logic Gate
KW - Spin-wave
UR - http://www.scopus.com/inward/record.url?scp=85098875426&partnerID=8YFLogxK
U2 - 10.1109/ICCD50377.2020.00062
DO - 10.1109/ICCD50377.2020.00062
M3 - Conference contribution
AN - SCOPUS:85098875426
SN - 978-1-7281-9711-1
T3 - 2020 IEEE 38TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD 2020)
SP - 332
EP - 335
BT - 2020 IEEE 38th International Conference on Computer Design (ICCD)
A2 - Guerrero , J.
PB - IEEE
CY - Piscataway
T2 - 38th IEEE International Conference on Computer Design, ICCD 2020
Y2 - 18 October 2020 through 21 October 2020
ER -