6.2 A 4-Way Doherty Digital Transmitter Featuring 50%-LO Signed IQ Interleave Upconversion with more than 27dBm Peak Power and 40% Drain Efficiency at 10dB Power Back-Off Operating in the 5GHz Band

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Abstract

Recently, digital transmitters (DTXs) that feature arrays of controlled digital PA (DPA) cells have become increasingly popular since they directly benefit from nanoscale CMOS technology, yielding reduced die area and highly efficient operation [1] -[6]. For wideband applications, I/Q DTXs are considered superior over their polar counterparts due to their linear I/Q operation, which avoids bandwidth expansion. Nevertheless, I/Q DTXs can suffer from the interaction between their I and Q paths, especially at higher power levels, giving rise to an I/Q image and nonlinearity. To tackle this issue, an IQ interleaved upconverter has been introduced [1]. However, its 25%-LO requirement restricts the operational frequency to below 5GHz. The diamond-shaped mapping technique, presented in [2], uses 50% LOs and a different I and Q combining method but suffers from nonlinearity due to a clipping operation. Besides, the large peak-to-average power ratio (PAPR) in modern wireless standards requires the DTX to operate in deep power back-off (DPBO), degrading its average efficiency. To target applications requiring large modulation bandwidth, high spectral purity and average efficiency, we present a DTX with a signed IQ interleaved upconversion approach based on 50%-LO clock distribution, which enables close to perfect orthogonal I/Q summation. To enhance its average efficiency, a compact, 4-way Doherty DPA architecture is introduced.

Original languageEnglish
Title of host publication2021 IEEE International Solid-State Circuits Conference, ISSCC 2021 - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages92-94
Number of pages3
ISBN (Electronic)9781728195490
DOIs
Publication statusPublished - 2021
Event2021 IEEE International Solid-State Circuits Conference, ISSCC 2021 - San Francisco, United States
Duration: 13 Feb 202122 Feb 2021

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume64
ISSN (Print)0193-6530

Conference

Conference2021 IEEE International Solid-State Circuits Conference, ISSCC 2021
CountryUnited States
CitySan Francisco
Period13/02/2122/02/21

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