A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8 #x2013;19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS

C.C. Li; T.H. Tsai; M.S. Yuan; C.C. Liao; C.H. Chang; T.C. Huang; H.Y. Liao; C.T. Lu; H.Y. Kuo; K. Hsieh; M Chen; A. Ronchini Ximenes; R. B. Staszewski

doi:10.1109/VLSIC.2016.7573551

A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8 #x2013;19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS

C.C. Li, T.H. Tsai, M.S. Yuan, C.C. Liao, C.H. Chang, T.C. Huang, H.Y. Liao, C.T. Lu, H.Y. Kuo, K. Hsieh, M Chen, A. Ronchini Ximenes, R. B. Staszewski

Electronics

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

11 Citations (Scopus)

Abstract

A tiny LC-tank-based ADPLL in 10nm FinFET CMOS achieves an area comparable to that of inverter-based ring-oscillator PLLs. A DCO occupying 0.016mm2 uses a controllable multi-turn magnetic coupling transformer to extend its tuning range to 10.8-19.3GHz (56.5%). A diversity of fine-tune capacitor banks limits the max/min step-size ratio to 2.3×. A new metastability-resolution scheme allows to use the frequency reference (FREF) clock directly instead of a retimed FREF (CKR) of conventional ADPLLs. A low-complexity estimator calculates inverse of the TDC. The fractional phase jitter (725fs) reaches sub-ps for the first time among PLLs of <;0.1mm2. Frequency pushing is 1.8%/V, which is at least 50× better than in traditional ring-type PLLs.

Original language	English
Title of host publication	2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)
Place of Publication	Piscataway
Publisher	IEEE
Pages	1-2
Number of pages	2
ISBN (Electronic)	978-1-5090-0635-9
DOIs	https://doi.org/10.1109/VLSIC.2016.7573551
Publication status	Published - 22 Sept 2016
Event	30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 - Honolulu, United States Duration: 14 Jun 2016 → 17 Jun 2016

Conference

Conference	30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016
Country/Territory	United States
City	Honolulu
Period	14/06/16 → 17/06/16

Keywords

CMOS integrated circuits
MOSFET circuits
digital phase locked loops
transformers
DCO
FinFET CMOS
LC-tank-based ADPLL
capacitor banks
fractional-N all-digital PLL
frequency 10.8 GHz to 19.3 GHz
frequency reference clock
inverter-based ring-oscillator PLL
magnetic coupling transformer
metastability-resolution scheme
size 10 nm
time 725 fs
Capacitors
Clocks
FinFETs
Jitter
Phase locked loops
Q-factor
Tuning

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10.1109/VLSIC.2016.7573551

Cite this

Li, C. C., Tsai, T. H., Yuan, M. S., Liao, C. C., Chang, C. H., Huang, T. C., Liao, H. Y., Lu, C. T., Kuo, H. Y., Hsieh, K., Chen, M., Ronchini Ximenes, A., & Staszewski, R. B. (2016). A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8 #x2013;19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS. In 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) (pp. 1-2). IEEE. https://doi.org/10.1109/VLSIC.2016.7573551

@inproceedings{ff9b6d1089994b57822beacd7930a751,

title = "A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8 #x2013;19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS",

abstract = "A tiny LC-tank-based ADPLL in 10nm FinFET CMOS achieves an area comparable to that of inverter-based ring-oscillator PLLs. A DCO occupying 0.016mm2 uses a controllable multi-turn magnetic coupling transformer to extend its tuning range to 10.8-19.3GHz (56.5%). A diversity of fine-tune capacitor banks limits the max/min step-size ratio to 2.3×. A new metastability-resolution scheme allows to use the frequency reference (FREF) clock directly instead of a retimed FREF (CKR) of conventional ADPLLs. A low-complexity estimator calculates inverse of the TDC. The fractional phase jitter (725fs) reaches sub-ps for the first time among PLLs of <;0.1mm2. Frequency pushing is 1.8%/V, which is at least 50× better than in traditional ring-type PLLs.",

keywords = "CMOS integrated circuits, MOSFET circuits, digital phase locked loops, transformers, DCO, FinFET CMOS, LC-tank-based ADPLL, capacitor banks, fractional-N all-digital PLL, frequency 10.8 GHz to 19.3 GHz, frequency reference clock, inverter-based ring-oscillator PLL, magnetic coupling transformer, metastability-resolution scheme, size 10 nm, time 725 fs, Capacitors, Clocks, FinFETs, Jitter, Phase locked loops, Q-factor, Tuning",

author = "C.C. Li and T.H. Tsai and M.S. Yuan and C.C. Liao and C.H. Chang and T.C. Huang and H.Y. Liao and C.T. Lu and H.Y. Kuo and K. Hsieh and M Chen and {Ronchini Ximenes}, A. and Staszewski, {R. B.}",

year = "2016",

month = sep,

day = "22",

doi = "10.1109/VLSIC.2016.7573551",

language = "English",

pages = "1--2",

booktitle = "2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)",

publisher = "IEEE",

address = "United States",

note = "30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 ; Conference date: 14-06-2016 Through 17-06-2016",

}

Li, CC, Tsai, TH, Yuan, MS, Liao, CC, Chang, CH, Huang, TC, Liao, HY, Lu, CT, Kuo, HY, Hsieh, K, Chen, M, Ronchini Ximenes, A & Staszewski, RB 2016, A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8 #x2013;19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS. in 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits). IEEE, Piscataway, pp. 1-2, 30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016, Honolulu, United States, 14/06/16. https://doi.org/10.1109/VLSIC.2016.7573551

A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8 #x2013;19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS. / Li, C.C.; Tsai, T.H.; Yuan, M.S. et al.
2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits). Piscataway: IEEE, 2016. p. 1-2.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

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AU - Tsai, T.H.

AU - Yuan, M.S.

AU - Liao, C.C.

AU - Chang, C.H.

AU - Huang, T.C.

AU - Liao, H.Y.

AU - Lu, C.T.

AU - Kuo, H.Y.

AU - Hsieh, K.

AU - Chen, M

AU - Ronchini Ximenes, A.

AU - Staszewski, R. B.

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N2 - A tiny LC-tank-based ADPLL in 10nm FinFET CMOS achieves an area comparable to that of inverter-based ring-oscillator PLLs. A DCO occupying 0.016mm2 uses a controllable multi-turn magnetic coupling transformer to extend its tuning range to 10.8-19.3GHz (56.5%). A diversity of fine-tune capacitor banks limits the max/min step-size ratio to 2.3×. A new metastability-resolution scheme allows to use the frequency reference (FREF) clock directly instead of a retimed FREF (CKR) of conventional ADPLLs. A low-complexity estimator calculates inverse of the TDC. The fractional phase jitter (725fs) reaches sub-ps for the first time among PLLs of <;0.1mm2. Frequency pushing is 1.8%/V, which is at least 50× better than in traditional ring-type PLLs.

AB - A tiny LC-tank-based ADPLL in 10nm FinFET CMOS achieves an area comparable to that of inverter-based ring-oscillator PLLs. A DCO occupying 0.016mm2 uses a controllable multi-turn magnetic coupling transformer to extend its tuning range to 10.8-19.3GHz (56.5%). A diversity of fine-tune capacitor banks limits the max/min step-size ratio to 2.3×. A new metastability-resolution scheme allows to use the frequency reference (FREF) clock directly instead of a retimed FREF (CKR) of conventional ADPLLs. A low-complexity estimator calculates inverse of the TDC. The fractional phase jitter (725fs) reaches sub-ps for the first time among PLLs of <;0.1mm2. Frequency pushing is 1.8%/V, which is at least 50× better than in traditional ring-type PLLs.

KW - CMOS integrated circuits

KW - MOSFET circuits

KW - digital phase locked loops

KW - transformers

KW - DCO

KW - FinFET CMOS

KW - LC-tank-based ADPLL

KW - capacitor banks

KW - fractional-N all-digital PLL

KW - frequency 10.8 GHz to 19.3 GHz

KW - frequency reference clock

KW - inverter-based ring-oscillator PLL

KW - magnetic coupling transformer

KW - metastability-resolution scheme

KW - size 10 nm

KW - time 725 fs

KW - Capacitors

KW - Clocks

KW - FinFETs

KW - Jitter

KW - Phase locked loops

KW - Q-factor

KW - Tuning

U2 - 10.1109/VLSIC.2016.7573551

DO - 10.1109/VLSIC.2016.7573551

M3 - Conference contribution

SP - 1

EP - 2

BT - 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)

PB - IEEE

CY - Piscataway

T2 - 30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016

Y2 - 14 June 2016 through 17 June 2016

ER -

A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8 #x2013;19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS

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Conference

Keywords

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