A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8 #x2013;19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS

C.C. Li, T.H. Tsai, M.S. Yuan, C.C. Liao, C.H. Chang, T.C. Huang, H.Y. Liao, C.T. Lu, H.Y. Kuo, K. Hsieh, M Chen, A. Ronchini Ximenes, R. B. Staszewski

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

9 Citations (Scopus)

Abstract

A tiny LC-tank-based ADPLL in 10nm FinFET CMOS achieves an area comparable to that of inverter-based ring-oscillator PLLs. A DCO occupying 0.016mm2 uses a controllable multi-turn magnetic coupling transformer to extend its tuning range to 10.8-19.3GHz (56.5%). A diversity of fine-tune capacitor banks limits the max/min step-size ratio to 2.3×. A new metastability-resolution scheme allows to use the frequency reference (FREF) clock directly instead of a retimed FREF (CKR) of conventional ADPLLs. A low-complexity estimator calculates inverse of the TDC. The fractional phase jitter (725fs) reaches sub-ps for the first time among PLLs of <;0.1mm2. Frequency pushing is 1.8%/V, which is at least 50× better than in traditional ring-type PLLs.
Original languageEnglish
Title of host publication2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)
Place of PublicationPiscataway
PublisherIEEE
Pages1-2
Number of pages2
ISBN (Electronic)978-1-5090-0635-9
DOIs
Publication statusPublished - 22 Sep 2016
Event30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 - Honolulu, United States
Duration: 14 Jun 201617 Jun 2016

Conference

Conference30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016
CountryUnited States
CityHonolulu
Period14/06/1617/06/16

Keywords

  • CMOS integrated circuits
  • MOSFET circuits
  • digital phase locked loops
  • transformers
  • DCO
  • FinFET CMOS
  • LC-tank-based ADPLL
  • capacitor banks
  • fractional-N all-digital PLL
  • frequency 10.8 GHz to 19.3 GHz
  • frequency reference clock
  • inverter-based ring-oscillator PLL
  • magnetic coupling transformer
  • metastability-resolution scheme
  • size 10 nm
  • time 725 fs
  • Capacitors
  • Clocks
  • FinFETs
  • Jitter
  • Phase locked loops
  • Q-factor
  • Tuning

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