A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW

Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Robert Bogdan Staszewski

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

3 Citations (Scopus)

Abstract

All-digital PLLs (ADPLL) based on a ring-oscillator (RO) provide very fast settling, but they suffer from quantization (Q) noise due to discrete tuning of their digitally controlled oscillator (DCO). Although RO charge-pump PLLs (CP-PLL) do not exhibit Q-noise thanks to their continuous VCO tuning, they are quite slow and require huge VCO gain. We propose a hybrid-PLL in 7nm FinFET CMOS that combines the best advantages of ADPLL and CP-PLL with a periodical phase realignment by the reference clock. It covers 0.2GHz-4GHz with 0.619ps integrated jitter and settles in 0.6us.

Original languageEnglish
Title of host publication2018 Symposium on VLSI Circuits Digest of Technical Papers
Place of PublicationPiscataway, NJ
PublisherIEEE
Pages183-184
Number of pages2
Volume2018-June
ISBN (Electronic)978-1-5386-4214-6
DOIs
Publication statusPublished - 22 Oct 2018
Externally publishedYes
Event2018 Symposia on VLSI Technology and Circuits: 2018 VLSI Technology Symposium - 2018 VLSI Circuits - Hilton Hawaiian Village, Honolulu, United States
Duration: 18 Jun 201822 Jun 2018

Conference

Conference2018 Symposia on VLSI Technology and Circuits
CountryUnited States
CityHonolulu
Period18/06/1822/06/18

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