A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference

Min Shueh Yuan; Chao Chieh Li; Chia Chun Liao; Yu Tso Lin; Chih Hsien Chang; Robert Bogdan Staszewski

doi:10.1109/ISSCC.2018.8310377

A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference

Min Shueh Yuan, Chao Chieh Li, Chia Chun Liao, Yu Tso Lin, Chih Hsien Chang, Robert Bogdan Staszewski

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

10 Citations (Scopus)

Abstract

The current paradigm of frequency synthesis for short-range wireless transceivers, such as BLE, is to use a crystal oscillator (XO) in the tens-of-MHz range as a frequency reference (FREF) to phase lock an RF oscillator [1-4]. This ensures a sufficiently wide PLL bandwidth of tens to hundreds of kHz to quickly acquire a new channel and to suppress lower-frequency phase noise (PN) of the RF oscillator. The latter requirement can be alleviated by substantially lowering the flicker PN of a digitally controlled oscillator (DCO) thus allowing to freeze its tuning word updates during receive (RX) packets and further directly FM-modulating the DCO during transmit (TX) packets [1]. However, an all-digital PLL (ADPLL) is still needed just to quickly settle the DCO to each new channel.

Original language	English
Title of host publication	2018 IEEE International Solid-State Circuits Conference, ISSCC 2018
Editors	L.J. Fujino
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	448-450
Number of pages	3
Volume	61
ISBN (Electronic)	978-1-5090-4940-0
DOIs	https://doi.org/10.1109/ISSCC.2018.8310377
Publication status	Published - 2018
Externally published	Yes
Event	65th IEEE International Solid-State Circuits Conference, ISSCC 2018 - San Francisco, United States Duration: 11 Feb 2018 → 15 Feb 2018

Conference

Conference	65th IEEE International Solid-State Circuits Conference, ISSCC 2018
Country/Territory	United States
City	San Francisco
Period	11/02/18 → 15/02/18

Keywords

Frequency modulation
Phase locked loops
Oscillators
Radio frequency
Bandwith
Tuning

Access to Document

10.1109/ISSCC.2018.8310377

Cite this

Yuan, M. S., Li, C. C., Liao, C. C., Lin, Y. T., Chang, C. H., & Staszewski, R. B. (2018). A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference. In L. J. Fujino (Ed.), 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018 (Vol. 61, pp. 448-450). IEEE. https://doi.org/10.1109/ISSCC.2018.8310377

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title = "A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference",

abstract = "The current paradigm of frequency synthesis for short-range wireless transceivers, such as BLE, is to use a crystal oscillator (XO) in the tens-of-MHz range as a frequency reference (FREF) to phase lock an RF oscillator [1-4]. This ensures a sufficiently wide PLL bandwidth of tens to hundreds of kHz to quickly acquire a new channel and to suppress lower-frequency phase noise (PN) of the RF oscillator. The latter requirement can be alleviated by substantially lowering the flicker PN of a digitally controlled oscillator (DCO) thus allowing to freeze its tuning word updates during receive (RX) packets and further directly FM-modulating the DCO during transmit (TX) packets [1]. However, an all-digital PLL (ADPLL) is still needed just to quickly settle the DCO to each new channel.",

keywords = "Frequency modulation, Phase locked loops, Oscillators, Radio frequency, Bandwith, Tuning",

author = "Yuan, {Min Shueh} and Li, {Chao Chieh} and Liao, {Chia Chun} and Lin, {Yu Tso} and Chang, {Chih Hsien} and Staszewski, {Robert Bogdan}",

year = "2018",

doi = "10.1109/ISSCC.2018.8310377",

language = "English",

volume = "61",

pages = "448--450",

editor = "L.J. Fujino",

booktitle = "2018 IEEE International Solid-State Circuits Conference, ISSCC 2018",

publisher = "IEEE",

address = "United States",

note = "65th IEEE International Solid-State Circuits Conference, ISSCC 2018 ; Conference date: 11-02-2018 Through 15-02-2018",

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Yuan, MS, Li, CC, Liao, CC, Lin, YT, Chang, CH & Staszewski, RB 2018, A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference. in LJ Fujino (ed.), 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018. vol. 61, IEEE, Piscataway, NJ, pp. 448-450, 65th IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, United States, 11/02/18. https://doi.org/10.1109/ISSCC.2018.8310377

A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference. / Yuan, Min Shueh; Li, Chao Chieh; Liao, Chia Chun et al.
2018 IEEE International Solid-State Circuits Conference, ISSCC 2018. ed. / L.J. Fujino. Vol. 61 Piscataway, NJ: IEEE, 2018. p. 448-450.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

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AU - Yuan, Min Shueh

AU - Li, Chao Chieh

AU - Liao, Chia Chun

AU - Lin, Yu Tso

AU - Chang, Chih Hsien

AU - Staszewski, Robert Bogdan

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N2 - The current paradigm of frequency synthesis for short-range wireless transceivers, such as BLE, is to use a crystal oscillator (XO) in the tens-of-MHz range as a frequency reference (FREF) to phase lock an RF oscillator [1-4]. This ensures a sufficiently wide PLL bandwidth of tens to hundreds of kHz to quickly acquire a new channel and to suppress lower-frequency phase noise (PN) of the RF oscillator. The latter requirement can be alleviated by substantially lowering the flicker PN of a digitally controlled oscillator (DCO) thus allowing to freeze its tuning word updates during receive (RX) packets and further directly FM-modulating the DCO during transmit (TX) packets [1]. However, an all-digital PLL (ADPLL) is still needed just to quickly settle the DCO to each new channel.

AB - The current paradigm of frequency synthesis for short-range wireless transceivers, such as BLE, is to use a crystal oscillator (XO) in the tens-of-MHz range as a frequency reference (FREF) to phase lock an RF oscillator [1-4]. This ensures a sufficiently wide PLL bandwidth of tens to hundreds of kHz to quickly acquire a new channel and to suppress lower-frequency phase noise (PN) of the RF oscillator. The latter requirement can be alleviated by substantially lowering the flicker PN of a digitally controlled oscillator (DCO) thus allowing to freeze its tuning word updates during receive (RX) packets and further directly FM-modulating the DCO during transmit (TX) packets [1]. However, an all-digital PLL (ADPLL) is still needed just to quickly settle the DCO to each new channel.

KW - Frequency modulation

KW - Phase locked loops

KW - Oscillators

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KW - Bandwith

KW - Tuning

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BT - 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018

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ER -

Yuan MS, Li CC, Liao CC, Lin YT, Chang CH, Staszewski RB. A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference. In Fujino LJ, editor, 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018. Vol. 61. Piscataway, NJ: IEEE. 2018. p. 448-450 doi: 10.1109/ISSCC.2018.8310377

A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference

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Conference

Keywords

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