A 0.5-V 1.6-mW 2.4-GHz Fractional-N All-Digital PLL for Bluetooth LE With PVT-Insensitive TDC Using Switched-Capacitor Doubler in 28-nm CMOS

Naser Pourmousavian, Feng Wei Kuo, Teerachot Siriburanon, Masoud Babaie, Robert Bogdan Staszewski

Research output: Contribution to journalArticleScientificpeer-review

20 Citations (Scopus)
65 Downloads (Pure)

Abstract

This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5-V supply. While its digitally controlled oscillator (DCO) runs directly at 0.5 V, an internal switched-capacitor dc-dc converter ``doubles'' the supply voltage to all the digital circuitry and particularly regulates the time-to-digital converter (TDC) supply to stabilize its resolution, thus maintaining fixed in-band phase noise (PN) across process, voltage, and temperature (PVT). The ADPLL supports a two-point modulation and forms a Bluetooth low-energy (BLE) transmitter realized in 28-nm CMOS. It maintains in-band PN of -106 dBc/Hz [figure of merit (FoM) of -239.2 dB] and rms jitter of 0.86 ps while dissipating only 1.6 mW at 40-MHz reference. The power consumption reduces to 0.8 mW during the BLE transmission when the DCO switches to open loop.

Original languageEnglish
Pages (from-to)2572-2583
Number of pages12
JournalIEEE Journal of Solid State Circuits
Volume53
Issue number9
DOIs
Publication statusPublished - 2018

Keywords

  • All-digital PLL (ADPLL)
  • and temperature (PVT) insensitive
  • Bluetooth
  • Bluetooth low energy (BLE)
  • Calibration
  • Clocks
  • Delays
  • digitally controlled oscillator (DCO)
  • Internet of Things (IoT)
  • Oscillators
  • Phase locked loops
  • process
  • regulator
  • switched-capacitor (SC) dc-dc doubler.
  • voltage
  • Voltage control

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