A 0.5V 1.6mW 2.4GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28nm CMOS

Feng-Wei Kuo, Seyednaser Pourmousavian, Teerachot Siriburanon, Ron Chen, Lan-chou Cho, Chewn-Pu Jou, Fu-Lung Hsueh, Robert Bogdan Staszewski

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

10 Citations (Scopus)

Abstract

This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5 V supply. While its DCO runs directly at 0.5 V, a switched-capacitor DC-DC converter doubles the supply voltage to all the digital circuitry and regulates the TDC supply to stabilize its resolution thus maintaining fixed inband phase noise (PN) across PVT. The ADPLL supports a 2-point modulation and forms a Bluetooth LE (BLE) transmitter realized in 28 nm CMOS. It achieves in-band PN of -106 dBc/Hz (FoM of -239.2 dB) and RMS jitter of 0.86ps while dissipating only 1.6mW at 40 MHz reference. The power consumption reduces to 0.8 mW during BLE transmission when the DCO switches to open-loop.
Original languageEnglish
Title of host publicationDigest of Technical Papers - 2017 Symposium on VLSI Circuits
Place of PublicationPiscataway, NJ
PublisherIEEE
PagesC178-C179
Number of pages2
ISBN (Electronic)978-4-86348-614-0
ISBN (Print)978-4-86348-606-5
DOIs
Publication statusPublished - 2017
Externally publishedYes
Event2017 Symposium on VLSI Technology and Circuits: 2017 VLSI Technology Symposium - 2017 VLSI Circuits Symposium - Kyoto, Japan
Duration: 5 Jun 20178 Jun 2017
http://vlsisymposium.org/2017/

Conference

Conference2017 Symposium on VLSI Technology and Circuits
CountryJapan
CityKyoto
Period5/06/178/06/17
Internet address

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