A 0.5V 1.6mW 2.4GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28nm CMOS

Feng-Wei Kuo; Seyednaser Pourmousavian; Teerachot Siriburanon; Ron Chen; Lan-chou Cho; Chewn-Pu Jou; Fu-Lung Hsueh; Robert Bogdan Staszewski

doi:10.23919/VLSIC.2017.8008472

A 0.5V 1.6mW 2.4GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28nm CMOS

Feng-Wei Kuo, Seyednaser Pourmousavian, Teerachot Siriburanon, Ron Chen, Lan-chou Cho, Chewn-Pu Jou, Fu-Lung Hsueh, Robert Bogdan Staszewski

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

16 Citations (Scopus)

Abstract

This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5 V supply. While its DCO runs directly at 0.5 V, a switched-capacitor DC-DC converter doubles the supply voltage to all the digital circuitry and regulates the TDC supply to stabilize its resolution thus maintaining fixed inband phase noise (PN) across PVT. The ADPLL supports a 2-point modulation and forms a Bluetooth LE (BLE) transmitter realized in 28 nm CMOS. It achieves in-band PN of -106 dBc/Hz (FoM of -239.2 dB) and RMS jitter of 0.86ps while dissipating only 1.6mW at 40 MHz reference. The power consumption reduces to 0.8 mW during BLE transmission when the DCO switches to open-loop.

Original language	English
Title of host publication	Digest of Technical Papers - 2017 Symposium on VLSI Circuits
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	C178-C179
Number of pages	2
ISBN (Electronic)	978-4-86348-614-0
ISBN (Print)	978-4-86348-606-5
DOIs	https://doi.org/10.23919/VLSIC.2017.8008472
Publication status	Published - 2017
Externally published	Yes
Event	2017 Symposium on VLSI Technology and Circuits: 2017 VLSI Technology Symposium - 2017 VLSI Circuits Symposium - Kyoto, Japan Duration: 5 Jun 2017 → 8 Jun 2017 http://vlsisymposium.org/2017/

Conference

Conference	2017 Symposium on VLSI Technology and Circuits
Country/Territory	Japan
City	Kyoto
Period	5/06/17 → 8/06/17
Internet address	http://vlsisymposium.org/2017/

Bibliographical note

C14-1

Access to Document

10.23919/VLSIC.2017.8008472

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Kuo, F.-W., Pourmousavian, S., Siriburanon, T., Chen, R., Cho, L., Jou, C.-P., Hsueh, F.-L., & Staszewski, R. B. (2017). A 0.5V 1.6mW 2.4GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28nm CMOS. In Digest of Technical Papers - 2017 Symposium on VLSI Circuits (pp. C178-C179). IEEE. https://doi.org/10.23919/VLSIC.2017.8008472

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title = "A 0.5V 1.6mW 2.4GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28nm CMOS",

abstract = "This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5 V supply. While its DCO runs directly at 0.5 V, a switched-capacitor DC-DC converter doubles the supply voltage to all the digital circuitry and regulates the TDC supply to stabilize its resolution thus maintaining fixed inband phase noise (PN) across PVT. The ADPLL supports a 2-point modulation and forms a Bluetooth LE (BLE) transmitter realized in 28 nm CMOS. It achieves in-band PN of -106 dBc/Hz (FoM of -239.2 dB) and RMS jitter of 0.86ps while dissipating only 1.6mW at 40 MHz reference. The power consumption reduces to 0.8 mW during BLE transmission when the DCO switches to open-loop.",

author = "Feng-Wei Kuo and Seyednaser Pourmousavian and Teerachot Siriburanon and Ron Chen and Lan-chou Cho and Chewn-Pu Jou and Fu-Lung Hsueh and Staszewski, {Robert Bogdan}",

note = "C14-1; 2017 Symposium on VLSI Technology and Circuits : 2017 VLSI Technology Symposium - 2017 VLSI Circuits Symposium ; Conference date: 05-06-2017 Through 08-06-2017",

year = "2017",

doi = "10.23919/VLSIC.2017.8008472",

language = "English",

isbn = "978-4-86348-606-5",

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booktitle = "Digest of Technical Papers - 2017 Symposium on VLSI Circuits",

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Kuo, F-W, Pourmousavian, S, Siriburanon, T, Chen, R, Cho, L, Jou, C-P, Hsueh, F-L & Staszewski, RB 2017, A 0.5V 1.6mW 2.4GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28nm CMOS. in Digest of Technical Papers - 2017 Symposium on VLSI Circuits. IEEE, Piscataway, NJ, pp. C178-C179, 2017 Symposium on VLSI Technology and Circuits, Kyoto, Japan, 5/06/17. https://doi.org/10.23919/VLSIC.2017.8008472

A 0.5V 1.6mW 2.4GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28nm CMOS. / Kuo, Feng-Wei; Pourmousavian, Seyednaser; Siriburanon, Teerachot et al.
Digest of Technical Papers - 2017 Symposium on VLSI Circuits. Piscataway, NJ: IEEE, 2017. p. C178-C179.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

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AU - Kuo, Feng-Wei

AU - Pourmousavian, Seyednaser

AU - Siriburanon, Teerachot

AU - Chen, Ron

AU - Cho, Lan-chou

AU - Jou, Chewn-Pu

AU - Hsueh, Fu-Lung

AU - Staszewski, Robert Bogdan

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PY - 2017

Y1 - 2017

N2 - This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5 V supply. While its DCO runs directly at 0.5 V, a switched-capacitor DC-DC converter doubles the supply voltage to all the digital circuitry and regulates the TDC supply to stabilize its resolution thus maintaining fixed inband phase noise (PN) across PVT. The ADPLL supports a 2-point modulation and forms a Bluetooth LE (BLE) transmitter realized in 28 nm CMOS. It achieves in-band PN of -106 dBc/Hz (FoM of -239.2 dB) and RMS jitter of 0.86ps while dissipating only 1.6mW at 40 MHz reference. The power consumption reduces to 0.8 mW during BLE transmission when the DCO switches to open-loop.

AB - This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5 V supply. While its DCO runs directly at 0.5 V, a switched-capacitor DC-DC converter doubles the supply voltage to all the digital circuitry and regulates the TDC supply to stabilize its resolution thus maintaining fixed inband phase noise (PN) across PVT. The ADPLL supports a 2-point modulation and forms a Bluetooth LE (BLE) transmitter realized in 28 nm CMOS. It achieves in-band PN of -106 dBc/Hz (FoM of -239.2 dB) and RMS jitter of 0.86ps while dissipating only 1.6mW at 40 MHz reference. The power consumption reduces to 0.8 mW during BLE transmission when the DCO switches to open-loop.

U2 - 10.23919/VLSIC.2017.8008472

DO - 10.23919/VLSIC.2017.8008472

M3 - Conference contribution

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SP - C178-C179

BT - Digest of Technical Papers - 2017 Symposium on VLSI Circuits

PB - IEEE

CY - Piscataway, NJ

T2 - 2017 Symposium on VLSI Technology and Circuits

Y2 - 5 June 2017 through 8 June 2017

ER -

A 0.5V 1.6mW 2.4GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28nm CMOS

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