Abstract
This article presents an energy-efficient dual- RC frequency reference intended for wireless sensor nodes. It consists of a digital frequency-locked loop (FLL) in which the frequency of a digitally controlled oscillator (DCO) is locked to a temperature-independent phase shift derived from two different RC poly-phase filters (PPFs). Phase shifts with complementary temperature coefficients (TCs) are generated by using PPFs made from different resistor types (p-poly and silicided p-poly). The phase shift of each filter is determined by a zero-crossing (ZC) detector and then digitized by a digital phase-domain ΔΣ modulator ( Φ - ΔΣM ). The results are then combined in the digital domain via fixed polynomials to produce a temperature-independent phase shift. This highly digital architecture enables the use of a sub-1-V supply voltage and enhances energy and area efficiency. The 28-MHz frequency reference occupies 0.06 mm2 in a 65-nm CMOS process. It achieves a period jitter of 7 ps ( 1σ ) and draws 142 μW from a 0.9-V supply, which corresponds to an energy consumption of 5 pJ/cycle. Furthermore, it achieves ±200 ppm inaccuracy from −40∘C to 85 ∘C after a two-point trim.
Original language | English |
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Article number | 9665815 |
Pages (from-to) | 2418-2428 |
Number of pages | 11 |
Journal | IEEE Journal of Solid-State Circuits |
Volume | 57 |
Issue number | 8 |
DOIs | |
Publication status | Published - 2022 |
Bibliographical note
Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-careOtherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.
Keywords
- CMOS frequency reference
- digital frequency-locked loop (FLL)
- digital phase-domain ΔΣ modulator (ϕ-ΔΣM)
- digitally assisted
- RC poly-phase filter (PPF)
- temperature compensation
- trimming
- wireless sensor node
- zero-crossing (ZC) detector.