A 1-3 GHz I/Q Interleaved Direct-Digital RF Modulator As A Driver for A Common-Gate PA in 40 nm CMOS

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Abstract

We present a 1-3 GHz, 2×13-bit I/Q interleaved direct-digital RF modulator (DDRM) realized in 40 nm CMOS technology as a driver for an external common-gate (CG) power amplifier (PA). The proposed digital-intensive quadrature up-converter features a pair of novel current-steering mixing DACs with an additional leakage path to boost the efficiency of the external CG PA. The realized DDRM also employs IQ-interleaving, harmonic rejection, and dynamic biasing to improve its spectral purity, in-band linearity, and system efficiency. The proposed digital up-converter prototype provides standalone more than 19.6 dBm RF peak output power. Without using any digital pre-distortion, it achieves an ACLR of-44.5 dBc and an EVM of-35 dB, when applying an 80 MHz 256 QAM signal at 2.4 GHz.

Original languageEnglish
Title of host publicationRFIC 2020 - 2020 IEEE Radio Frequency Integrated Circuits Symposium
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages287-290
Number of pages4
ISBN (Electronic)9781728168098
DOIs
Publication statusPublished - 2020
Event2020 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2020 - Virtual, Los Angeles, United States
Duration: 4 Aug 20206 Aug 2020

Publication series

NameDigest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
Volume2020-August
ISSN (Print)1529-2517

Conference

Conference2020 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2020
CountryUnited States
CityVirtual, Los Angeles
Period4/08/206/08/20

Keywords

  • CG PA
  • DDRM
  • DPD-free
  • dynamic biasing
  • harmonic rejection
  • IQ-Interleaving
  • PA driver
  • RF-DAC

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