TY - JOUR
T1 - A 1-GS/s 6–8-b Cryo-CMOS SAR ADC for Quantum Computing
AU - Kiene, G.
AU - Overwater, R.W.J.
AU - Catania, Alessandro
AU - Gunaputi Sreenivasulu, A.M.
AU - Bruschi, Paolo
AU - Charbon-Iwasaki-Charbon, E.
AU - Babaie, M.
AU - Sebastiano, F.
PY - 2023
Y1 - 2023
N2 - This article presents a two-times interleaved, loop-unrolled SAR analog-to-digital converter (ADC) operational from 300 down to 4.2 K. The 6–8-bit resolution and the sampling speed up to 1 GS/s are targeted at digitizing the multi-channel frequency-multiplexed input in a spin-qubit reflectometry readout for quantum computing. To optimize the circuit for the altered device behavior at cryogenic temperatures, a modified common-mode switching scheme is adopted as well as a flexible calibration. The design is implemented in 40-nm CMOS technology and achieves 36.2-dB signal to noise and distortion ratio (SNDR) for Nyquist input at 4.2 K while maintaining a Walden figure of merit (FOMW) of 200 pJ/conv-step (for a 10.8-mW power consumption), including the clock receiver, and 15 pJ/conv-step (for a 0.8-mW power consumption) for just the core ADC. With these specifications, the ADC can support the simultaneous readout of 20 qubit channels with a power consumption of 0.5 mW/qubit, thus advancing toward the full integration of the cryogenic readout for future large-scale quantum processors.
AB - This article presents a two-times interleaved, loop-unrolled SAR analog-to-digital converter (ADC) operational from 300 down to 4.2 K. The 6–8-bit resolution and the sampling speed up to 1 GS/s are targeted at digitizing the multi-channel frequency-multiplexed input in a spin-qubit reflectometry readout for quantum computing. To optimize the circuit for the altered device behavior at cryogenic temperatures, a modified common-mode switching scheme is adopted as well as a flexible calibration. The design is implemented in 40-nm CMOS technology and achieves 36.2-dB signal to noise and distortion ratio (SNDR) for Nyquist input at 4.2 K while maintaining a Walden figure of merit (FOMW) of 200 pJ/conv-step (for a 10.8-mW power consumption), including the clock receiver, and 15 pJ/conv-step (for a 0.8-mW power consumption) for just the core ADC. With these specifications, the ADC can support the simultaneous readout of 20 qubit channels with a power consumption of 0.5 mW/qubit, thus advancing toward the full integration of the cryogenic readout for future large-scale quantum processors.
KW - Analog-to-digital converter (ADC)
KW - cryo-CMOS
KW - loop unrolled
KW - quantum computing
KW - SAR
KW - variable common mode
UR - http://www.scopus.com/inward/record.url?scp=85148478270&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2023.3237603
DO - 10.1109/JSSC.2023.3237603
M3 - Article
JO - IEEE Journal of Solid State Circuits
JF - IEEE Journal of Solid State Circuits
SN - 0018-9200
ER -