A 1-GS/s 6–8-b Cryo-CMOS SAR ADC for Quantum Computing

G. Kiene*, R.W.J. Overwater, Alessandro Catania, A.M. Gunaputi Sreenivasulu, Paolo Bruschi, E. Charbon-Iwasaki-Charbon, M. Babaie, F. Sebastiano

*Corresponding author for this work

Research output: Contribution to journalArticleScientificpeer-review

3 Citations (Scopus)
102 Downloads (Pure)

Abstract

This article presents a two-times interleaved, loop-unrolled SAR analog-to-digital converter (ADC) operational from 300 down to 4.2 K. The 6-8-bit resolution and the sampling speed up to 1 GS/s are targeted at digitizing the multi-channel frequency-multiplexed input in a spin-qubit reflectometry readout for quantum computing. To optimize the circuit for the altered device behavior at cryogenic temperatures, a modified common-mode switching scheme is adopted as well as a flexible calibration. The design is implemented in 40-nm CMOS technology and achieves 36.2-dB signal to noise and distortion ratio (SNDR) for Nyquist input at 4.2 K while maintaining a Walden figure of merit (FOM textsubscript W) of 200 pJ/conv-step (for a 10.8-mW power consumption), including the clock receiver, and 15 pJ/conv-step (for a 0.8-mW power consumption) for just the core ADC. With these specifications, the ADC can support the simultaneous readout of 20 qubit channels with a power consumption of 0.5 mW/qubit, thus advancing toward the full integration of the cryogenic readout for future large-scale quantum processors.

Original languageEnglish
Pages (from-to)2016-2027
Number of pages12
JournalIEEE Journal of Solid State Circuits
Volume58
Issue number7
DOIs
Publication statusPublished - 2023

Keywords

  • Analog-to-digital converter (ADC)
  • cryo-CMOS
  • loop unrolled
  • quantum computing
  • SAR
  • variable common mode

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