A 10 bit 5 MS/s column SAR ADC with digital error correction for CMOS image sensors

Shuang Xie, Albert Theuwissen

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This brief proposes a successive approximation register (SAR) analog-to-digital converter (ADC) whose readout speed is improved by 33%, through applying a digital error correction (DEC) method, compared to an alternative without using the DEC technique. The proposed addition-only DEC alleviates the ADC's incomplete settling errors, hence improving conversion rate while maintaining accuracy. It is based on a binary bridged SAR architecture with 4 redundant capacitors and conversion cycles, which ensure the ADC's linearity of 10 bit within a 5 bit accuracy's settling time. The proposed SAR keeps the same straightforward timing diagram as that in a conventional SAR ADC, incurring no offset to the ADC. Measurement results of 15 columns of SAR ADCs, sampling at 5 MS/s on the same CMOS image sensor (CIS) chip, show integral nonlinearity (INL) around 3 LSB (1LSB = 1 mV), when sampling at 5 MHz, after a proposed swift digital background calibration that incurs no additional hardware complexity. The CIS array read out by the proposed column-level SAR ADCs is measured reasonable photoelectron transfer characteristics.

Original languageEnglish
Article number8759916
Pages (from-to)984 - 988
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Issue number6
Publication statusPublished - 2020


  • ADC
  • analog-to-digital converter
  • CMOS image sensor
  • DEC
  • digital background calibration
  • digital error correction
  • SAR
  • successive approximation register

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