A 10-to-12 GHz 5 mW Charge-Sampling PLL Achieving 50 fsec RMS Jitter,-258.9 dB FOM and-65 dBc Reference Spur

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Abstract

This paper presents a charge-sampling PLL (CSPLL), that demonstrates the best reported jitter-power FOM of-258.9 dB thanks to its high phase-detection gain and to the removal of the power-hungry buffer driving the phase detector. It also achieves-65 dBc of reference spur by both minimizing the modulated capacitance seen by the VCO tank and reducing the duty cycle of the sampling clock. Without requiring any RF dividers, a 50 μW frequency tracking loop is also introduced to robustly lock the CSPLL to a 100 MHz reference. Fabricated in 40-nm CMOS, the 0.13 mm2 CSPLL achieves an RMS jitter of 50 fsec at 11.4 GHz while consuming 5 mW.

Original languageEnglish
Title of host publicationRFIC 2020 - 2020 IEEE Radio Frequency Integrated Circuits Symposium
Place of PublicationPiscataway, NJ, USA
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages15-18
Number of pages4
ISBN (Electronic)9781728168098
DOIs
Publication statusPublished - 2020
Event2020 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2020 - Virtual, Los Angeles, United States
Duration: 4 Aug 20206 Aug 2020

Publication series

NameDigest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
Volume2020-August
ISSN (Print)1529-2517

Conference

Conference2020 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2020
CountryUnited States
CityVirtual, Los Angeles
Period4/08/206/08/20

Keywords

  • charge-sampling phase detector
  • Charge-sampling PLL
  • divider-less frequency tracking loop
  • low-jitter

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