@inproceedings{50775705f4694e73a110fee3001a0bbb,
title = "A 10-to-12 GHz 5 mW Charge-Sampling PLL Achieving 50 fsec RMS Jitter,-258.9 dB FOM and-65 dBc Reference Spur",
abstract = "This paper presents a charge-sampling PLL (CSPLL), that demonstrates the best reported jitter-power FOM of-258.9 dB thanks to its high phase-detection gain and to the removal of the power-hungry buffer driving the phase detector. It also achieves-65 dBc of reference spur by both minimizing the modulated capacitance seen by the VCO tank and reducing the duty cycle of the sampling clock. Without requiring any RF dividers, a 50 μW frequency tracking loop is also introduced to robustly lock the CSPLL to a 100 MHz reference. Fabricated in 40-nm CMOS, the 0.13 mm2 CSPLL achieves an RMS jitter of 50 fsec at 11.4 GHz while consuming 5 mW.",
keywords = "charge-sampling phase detector, Charge-sampling PLL, divider-less frequency tracking loop, low-jitter",
author = "Jiang Gong and Fabio Sebastiano and Edoardo Charbon and Masoud Babaie",
note = "Accepted Author Manuscript; 2020 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2020 ; Conference date: 04-08-2020 Through 06-08-2020",
year = "2020",
doi = "10.1109/RFIC49505.2020.9218380",
language = "English",
series = "Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium",
publisher = "Institute of Electrical and Electronics Engineers (IEEE)",
pages = "15--18",
booktitle = "RFIC 2020 - 2020 IEEE Radio Frequency Integrated Circuits Symposium",
address = "United States",
}