A 10-to-12 GHz 5 mW Charge-Sampling PLL Achieving 50 fsec RMS Jitter,-258.9 dB FOM and-65 dBc Reference Spur

Jiang Gong; Fabio Sebastiano; Edoardo Charbon; Masoud Babaie

doi:10.1109/RFIC49505.2020.9218380

A 10-to-12 GHz 5 mW Charge-Sampling PLL Achieving 50 fsec RMS Jitter,-258.9 dB FOM and-65 dBc Reference Spur

Jiang Gong, Fabio Sebastiano, Edoardo Charbon, Masoud Babaie

Electronics

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

11 Citations (Scopus)

114 Downloads (Pure)

Abstract

This paper presents a charge-sampling PLL (CSPLL), that demonstrates the best reported jitter-power FOM of-258.9 dB thanks to its high phase-detection gain and to the removal of the power-hungry buffer driving the phase detector. It also achieves-65 dBc of reference spur by both minimizing the modulated capacitance seen by the VCO tank and reducing the duty cycle of the sampling clock. Without requiring any RF dividers, a 50 μW frequency tracking loop is also introduced to robustly lock the CSPLL to a 100 MHz reference. Fabricated in 40-nm CMOS, the 0.13 mm2 CSPLL achieves an RMS jitter of 50 fsec at 11.4 GHz while consuming 5 mW.

Original language	English
Title of host publication	RFIC 2020 - 2020 IEEE Radio Frequency Integrated Circuits Symposium
Place of Publication	Piscataway, NJ, USA
Publisher	IEEE
Pages	15-18
Number of pages	4
ISBN (Electronic)	9781728168098
DOIs	https://doi.org/10.1109/RFIC49505.2020.9218380
Publication status	Published - 2020
Event	2020 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2020 - Virtual, Los Angeles, United States Duration: 4 Aug 2020 → 6 Aug 2020

Publication series

Name	Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
Volume	2020-August
ISSN (Print)	1529-2517

Conference

Conference	2020 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2020
Country/Territory	United States
City	Virtual, Los Angeles
Period	4/08/20 → 6/08/20

Bibliographical note

Accepted Author Manuscript

Keywords

charge-sampling phase detector
Charge-sampling PLL
divider-less frequency tracking loop
low-jitter

Access to Document

10.1109/RFIC49505.2020.9218380

Jiang_RFIC2020Accepted author manuscript, 1.26 MB

Cite this

Gong, J., Sebastiano, F., Charbon, E., & Babaie, M. (2020). A 10-to-12 GHz 5 mW Charge-Sampling PLL Achieving 50 fsec RMS Jitter,-258.9 dB FOM and-65 dBc Reference Spur. In RFIC 2020 - 2020 IEEE Radio Frequency Integrated Circuits Symposium (pp. 15-18). Article 9218380 (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium; Vol. 2020-August). IEEE. https://doi.org/10.1109/RFIC49505.2020.9218380

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title = "A 10-to-12 GHz 5 mW Charge-Sampling PLL Achieving 50 fsec RMS Jitter,-258.9 dB FOM and-65 dBc Reference Spur",

abstract = "This paper presents a charge-sampling PLL (CSPLL), that demonstrates the best reported jitter-power FOM of-258.9 dB thanks to its high phase-detection gain and to the removal of the power-hungry buffer driving the phase detector. It also achieves-65 dBc of reference spur by both minimizing the modulated capacitance seen by the VCO tank and reducing the duty cycle of the sampling clock. Without requiring any RF dividers, a 50 μW frequency tracking loop is also introduced to robustly lock the CSPLL to a 100 MHz reference. Fabricated in 40-nm CMOS, the 0.13 mm2 CSPLL achieves an RMS jitter of 50 fsec at 11.4 GHz while consuming 5 mW.",

keywords = "charge-sampling phase detector, Charge-sampling PLL, divider-less frequency tracking loop, low-jitter",

author = "Jiang Gong and Fabio Sebastiano and Edoardo Charbon and Masoud Babaie",

note = "Accepted Author Manuscript; 2020 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2020 ; Conference date: 04-08-2020 Through 06-08-2020",

year = "2020",

doi = "10.1109/RFIC49505.2020.9218380",

language = "English",

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Gong, J, Sebastiano, F , Charbon, E & Babaie, M 2020, A 10-to-12 GHz 5 mW Charge-Sampling PLL Achieving 50 fsec RMS Jitter,-258.9 dB FOM and-65 dBc Reference Spur. in RFIC 2020 - 2020 IEEE Radio Frequency Integrated Circuits Symposium., 9218380, Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium, vol. 2020-August, IEEE, Piscataway, NJ, USA, pp. 15-18, 2020 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2020, Virtual, Los Angeles, United States, 4/08/20. https://doi.org/10.1109/RFIC49505.2020.9218380

A 10-to-12 GHz 5 mW Charge-Sampling PLL Achieving 50 fsec RMS Jitter,-258.9 dB FOM and-65 dBc Reference Spur. / Gong, Jiang; Sebastiano, Fabio ; Charbon, Edoardo et al.
RFIC 2020 - 2020 IEEE Radio Frequency Integrated Circuits Symposium. Piscataway, NJ, USA: IEEE, 2020. p. 15-18 9218380 (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium; Vol. 2020-August).

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

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AU - Babaie, Masoud

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N2 - This paper presents a charge-sampling PLL (CSPLL), that demonstrates the best reported jitter-power FOM of-258.9 dB thanks to its high phase-detection gain and to the removal of the power-hungry buffer driving the phase detector. It also achieves-65 dBc of reference spur by both minimizing the modulated capacitance seen by the VCO tank and reducing the duty cycle of the sampling clock. Without requiring any RF dividers, a 50 μW frequency tracking loop is also introduced to robustly lock the CSPLL to a 100 MHz reference. Fabricated in 40-nm CMOS, the 0.13 mm2 CSPLL achieves an RMS jitter of 50 fsec at 11.4 GHz while consuming 5 mW.

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Gong J, Sebastiano F , Charbon E , Babaie M. A 10-to-12 GHz 5 mW Charge-Sampling PLL Achieving 50 fsec RMS Jitter,-258.9 dB FOM and-65 dBc Reference Spur. In RFIC 2020 - 2020 IEEE Radio Frequency Integrated Circuits Symposium. Piscataway, NJ, USA: IEEE. 2020. p. 15-18. 9218380. (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium). doi: 10.1109/RFIC49505.2020.9218380

A 10-to-12 GHz 5 mW Charge-Sampling PLL Achieving 50 fsec RMS Jitter,-258.9 dB FOM and-65 dBc Reference Spur

Abstract

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Keywords

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