A 103fsrms 1.32mW 50MS/s 1.25MHz bandwidth two-step flash-¿¿ time-to-digital converter for ADPLL

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

14 Citations (Scopus)
Original languageEnglish
Title of host publicationProceedings of the 2015 IEEE Radio Frequency Integrated Circuits Symposium
EditorsF van Straten, S Mehta
Place of PublicationPiscataway
PublisherIEEE Society
Pages95-98
Number of pages4
ISBN (Print)978-1-4799-7642-3
DOIs
Publication statusPublished - 2015
EventRFIC 2015, Phoenix, USA - Piscataway
Duration: 17 May 201519 May 2015

Publication series

Name
PublisherIEEE

Conference

ConferenceRFIC 2015, Phoenix, USA
Period17/05/1519/05/15

Cite this

Wu, Y., Lu, P., & Staszewski, RB. (2015). A 103fsrms 1.32mW 50MS/s 1.25MHz bandwidth two-step flash-¿¿ time-to-digital converter for ADPLL. In F. van Straten, & S. Mehta (Eds.), Proceedings of the 2015 IEEE Radio Frequency Integrated Circuits Symposium (pp. 95-98). IEEE Society. https://doi.org/10.1109/RFIC.2015.7337713