A 103fsrms 1.32mW 50MS/s 1.25MHz bandwidth two-step flash-¿¿ time-to-digital converter for ADPLL

Y Wu; P Lu; RB Staszewski

doi:10.1109/RFIC.2015.7337713

A 103fsrms 1.32mW 50MS/s 1.25MHz bandwidth two-step flash-¿¿ time-to-digital converter for ADPLL

Electronics

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

16 Citations (Scopus)

Original language	English
Title of host publication	Proceedings of the 2015 IEEE Radio Frequency Integrated Circuits Symposium
Editors	F van Straten, S Mehta
Place of Publication	Piscataway
Publisher	IEEE Society
Pages	95-98
Number of pages	4
ISBN (Print)	978-1-4799-7642-3
DOIs	https://doi.org/10.1109/RFIC.2015.7337713
Publication status	Published - 2015
Event	RFIC 2015, Phoenix, USA - Piscataway Duration: 17 May 2015 → 19 May 2015

Publication series

Name
Publisher	IEEE

Conference

Conference	RFIC 2015, Phoenix, USA
Period	17/05/15 → 19/05/15

Bibliographical note

harvest

Access to Document

10.1109/RFIC.2015.7337713

Cite this

@inproceedings{c9f494e842ae43b9b313b72cf337d7fa,

title = "A 103fsrms 1.32mW 50MS/s 1.25MHz bandwidth two-step flash-¿¿ time-to-digital converter for ADPLL",

author = "Y Wu and P Lu and RB Staszewski",

note = "harvest; RFIC 2015, Phoenix, USA ; Conference date: 17-05-2015 Through 19-05-2015",

year = "2015",

doi = "10.1109/RFIC.2015.7337713",

language = "English",

isbn = "978-1-4799-7642-3",

publisher = "IEEE Society",

pages = "95--98",

editor = "{van Straten}, F and S Mehta",

booktitle = "Proceedings of the 2015 IEEE Radio Frequency Integrated Circuits Symposium",

}

A 103fsrms 1.32mW 50MS/s 1.25MHz bandwidth two-step flash-¿¿ time-to-digital converter for ADPLL. / Wu, Y; Lu, P; Staszewski, RB.
Proceedings of the 2015 IEEE Radio Frequency Integrated Circuits Symposium. ed. / F van Straten; S Mehta. Piscataway: IEEE Society, 2015. p. 95-98.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - A 103fsrms 1.32mW 50MS/s 1.25MHz bandwidth two-step flash-¿¿ time-to-digital converter for ADPLL

AU - Wu, Y

AU - Lu, P

AU - Staszewski, RB

N1 - harvest

PY - 2015

Y1 - 2015

U2 - 10.1109/RFIC.2015.7337713

DO - 10.1109/RFIC.2015.7337713

M3 - Conference contribution

SN - 978-1-4799-7642-3

SP - 95

EP - 98

BT - Proceedings of the 2015 IEEE Radio Frequency Integrated Circuits Symposium

A2 - van Straten, F

A2 - Mehta, S

PB - IEEE Society

CY - Piscataway

T2 - RFIC 2015, Phoenix, USA

Y2 - 17 May 2015 through 19 May 2015

ER -