A 1.22ps Integrated-Jitter 0.25-to-4GHz Fractional-N ADPLL in 16nm FinFET CMOS

TH Tsai; MS Yuan; CH Chang; CC Liao; CC Li; RB Staszewski

doi:10.1109/ISSCC.2015.7063025

A 1.22ps Integrated-Jitter 0.25-to-4GHz Fractional-N ADPLL in 16nm FinFET CMOS

TH Tsai, MS Yuan, CH Chang, CC Liao, CC Li, RB Staszewski

Electronics

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

37 Citations (Scopus)

Original language	English
Title of host publication	Digest of technical papers - 2015 IEEE International Solid-State Circuits Conference
Editors	M Romdhane
Place of Publication	Piscataway, NJ, USA
Publisher	IEEE
Pages	259-261
Number of pages	3
ISBN (Print)	978-1-4799-6223-5
DOIs	https://doi.org/10.1109/ISSCC.2015.7063025
Publication status	Published - 2015
Event	IEEE ISSCC 2015, San Francisco, CA, USA - Piscataway, NJ, USA Duration: 22 Feb 2015 → 26 Feb 2015

Publication series

Name
Publisher	IEEE

Conference

Conference	IEEE ISSCC 2015, San Francisco, CA, USA
Period	22/02/15 → 26/02/15

Bibliographical note

Harvest
Session 14.5

Access to Document

10.1109/ISSCC.2015.7063025

Cite this

@inproceedings{df21e05710d841e7b2d20242e311ad1c,

title = "A 1.22ps Integrated-Jitter 0.25-to-4GHz Fractional-N ADPLL in 16nm FinFET CMOS",

author = "TH Tsai and MS Yuan and CH Chang and CC Liao and CC Li and RB Staszewski",

note = "Harvest Session 14.5; IEEE ISSCC 2015, San Francisco, CA, USA ; Conference date: 22-02-2015 Through 26-02-2015",

year = "2015",

doi = "10.1109/ISSCC.2015.7063025",

language = "English",

isbn = "978-1-4799-6223-5",

publisher = "IEEE",

pages = "259--261",

editor = "M Romdhane",

booktitle = "Digest of technical papers - 2015 IEEE International Solid-State Circuits Conference",

address = "United States",

}

Tsai, TH, Yuan, MS, Chang, CH, Liao, CC, Li, CC & Staszewski, RB 2015, A 1.22ps Integrated-Jitter 0.25-to-4GHz Fractional-N ADPLL in 16nm FinFET CMOS. in M Romdhane (ed.), Digest of technical papers - 2015 IEEE International Solid-State Circuits Conference. IEEE, Piscataway, NJ, USA, pp. 259-261, IEEE ISSCC 2015, San Francisco, CA, USA, 22/02/15. https://doi.org/10.1109/ISSCC.2015.7063025

A 1.22ps Integrated-Jitter 0.25-to-4GHz Fractional-N ADPLL in 16nm FinFET CMOS. / Tsai, TH; Yuan, MS; Chang, CH et al.
Digest of technical papers - 2015 IEEE International Solid-State Circuits Conference. ed. / M Romdhane. Piscataway, NJ, USA: IEEE, 2015. p. 259-261.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - A 1.22ps Integrated-Jitter 0.25-to-4GHz Fractional-N ADPLL in 16nm FinFET CMOS

AU - Tsai, TH

AU - Yuan, MS

AU - Chang, CH

AU - Liao, CC

AU - Li, CC

AU - Staszewski, RB

N1 - Harvest Session 14.5

PY - 2015

Y1 - 2015

U2 - 10.1109/ISSCC.2015.7063025

DO - 10.1109/ISSCC.2015.7063025

M3 - Conference contribution

SN - 978-1-4799-6223-5

SP - 259

EP - 261

BT - Digest of technical papers - 2015 IEEE International Solid-State Circuits Conference

A2 - Romdhane, M

PB - IEEE

CY - Piscataway, NJ, USA

T2 - IEEE ISSCC 2015, San Francisco, CA, USA

Y2 - 22 February 2015 through 26 February 2015

ER -