A 1.33 mW, 1.6psrms-integrated-jitter, 1.8-2.7 GHz ring-oscillator-based fractional-n injection-locked DPLL for internet-of-things applications

Jiang Gong*, Yuming He, Ao Ba, Yao Hong Liu, Johan Dijkhuis, Stefano Traferro, Christian Bachmann, Kathleen Philips, Masoud Babaie

*Corresponding author for this work

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

10 Citations (Scopus)

Abstract

This paper presents a 1.8-2.7 GHz low-power ring-oscillator-based fractional-N injection-locked digital PLL (IL-DPLL) in 40-nm CMOS for Internet-of-Things clock generation. A two-path injection technique is proposed to improve the in-band phase noise and the integrated jitter of the implemented PLL by 6 dB and 1.8×, respectively. Furthermore, a digital foreground calibration is introduced to effectively reduce reference spurs in a short calibration time of 2 μs. In the worst-case channel, the proposed DPLL using a 64 MHz reference input shows a 1.6 ps integrated jitter, -43.6 dBc reference spur, -45.8 dBc fractional spur and 1 kHz frequency resolution while consuming 1.33 mW power.

Original languageEnglish
Title of host publicationProceedings of the 2018 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2018
EditorsAndre Hanke Hanke, Steven Turner
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages44-47
Number of pages4
Volume2018-June
ISBN (Print)978-153864545-1
DOIs
Publication statusPublished - 2018
Event2018 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2018 - Philadelphia, United States
Duration: 10 Jun 201812 Jun 2018

Conference

Conference2018 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2018
Country/TerritoryUnited States
CityPhiladelphia
Period10/06/1812/06/18

Keywords

  • fractional-N DPLL
  • injection locking
  • Internet-of-Things
  • reference spur
  • ring oscillator

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