A 1.33 mW, 1.6psrms-integrated-jitter, 1.8-2.7 GHz ring-oscillator-based fractional-n injection-locked DPLL for internet-of-things applications

Jiang Gong; Yuming He; Ao Ba; Yao Hong Liu; Johan Dijkhuis; Stefano Traferro; Christian Bachmann; Kathleen Philips; Masoud Babaie

doi:10.1109/RFIC.2018.8429041

A 1.33 mW, 1.6ps_rms-integrated-jitter, 1.8-2.7 GHz ring-oscillator-based fractional-n injection-locked DPLL for internet-of-things applications

Jiang Gong^*, Yuming He, Ao Ba, Yao Hong Liu, Johan Dijkhuis, Stefano Traferro, Christian Bachmann, Kathleen Philips, Masoud Babaie

^*Corresponding author for this work

Electronics

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

15 Citations (Scopus)

Abstract

This paper presents a 1.8-2.7 GHz low-power ring-oscillator-based fractional-N injection-locked digital PLL (IL-DPLL) in 40-nm CMOS for Internet-of-Things clock generation. A two-path injection technique is proposed to improve the in-band phase noise and the integrated jitter of the implemented PLL by 6 dB and 1.8×, respectively. Furthermore, a digital foreground calibration is introduced to effectively reduce reference spurs in a short calibration time of 2 μs. In the worst-case channel, the proposed DPLL using a 64 MHz reference input shows a 1.6 ps integrated jitter, -43.6 dBc reference spur, -45.8 dBc fractional spur and 1 kHz frequency resolution while consuming 1.33 mW power.

Original language	English
Title of host publication	Proceedings of the 2018 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2018
Editors	Andre Hanke Hanke, Steven Turner
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	44-47
Number of pages	4
Volume	2018-June
ISBN (Print)	978-153864545-1
DOIs	https://doi.org/10.1109/RFIC.2018.8429041
Publication status	Published - 2018
Event	2018 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2018 - Philadelphia, United States Duration: 10 Jun 2018 → 12 Jun 2018

Conference

Conference	2018 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2018
Country/Territory	United States
City	Philadelphia
Period	10/06/18 → 12/06/18

Keywords

fractional-N DPLL
injection locking
Internet-of-Things
reference spur
ring oscillator

Access to Document

10.1109/RFIC.2018.8429041

Cite this

Gong, J., He, Y., Ba, A., Liu, Y. H., Dijkhuis, J., Traferro, S., Bachmann, C., Philips, K., & Babaie, M. (2018). A 1.33 mW, 1.6ps_rms-integrated-jitter, 1.8-2.7 GHz ring-oscillator-based fractional-n injection-locked DPLL for internet-of-things applications. In A. H. Hanke, & S. Turner (Eds.), Proceedings of the 2018 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2018 (Vol. 2018-June, pp. 44-47). Article 8429041 Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/RFIC.2018.8429041

Gong, Jiang ; He, Yuming ; Ba, Ao et al. / A 1.33 mW, 1.6ps_rms-integrated-jitter, 1.8-2.7 GHz ring-oscillator-based fractional-n injection-locked DPLL for internet-of-things applications. Proceedings of the 2018 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2018. editor / Andre Hanke Hanke ; Steven Turner. Vol. 2018-June Institute of Electrical and Electronics Engineers (IEEE), 2018. pp. 44-47

@inproceedings{9eb9690d079f48c4ad2a1ae913689d56,

title = "A 1.33 mW, 1.6psrms-integrated-jitter, 1.8-2.7 GHz ring-oscillator-based fractional-n injection-locked DPLL for internet-of-things applications",

abstract = "This paper presents a 1.8-2.7 GHz low-power ring-oscillator-based fractional-N injection-locked digital PLL (IL-DPLL) in 40-nm CMOS for Internet-of-Things clock generation. A two-path injection technique is proposed to improve the in-band phase noise and the integrated jitter of the implemented PLL by 6 dB and 1.8×, respectively. Furthermore, a digital foreground calibration is introduced to effectively reduce reference spurs in a short calibration time of 2 μs. In the worst-case channel, the proposed DPLL using a 64 MHz reference input shows a 1.6 ps integrated jitter, -43.6 dBc reference spur, -45.8 dBc fractional spur and 1 kHz frequency resolution while consuming 1.33 mW power.",

keywords = "fractional-N DPLL, injection locking, Internet-of-Things, reference spur, ring oscillator",

author = "Jiang Gong and Yuming He and Ao Ba and Liu, {Yao Hong} and Johan Dijkhuis and Stefano Traferro and Christian Bachmann and Kathleen Philips and Masoud Babaie",

year = "2018",

doi = "10.1109/RFIC.2018.8429041",

language = "English",

isbn = "978-153864545-1",

volume = "2018-June",

pages = "44--47",

editor = "Hanke, {Andre Hanke} and Steven Turner",

booktitle = "Proceedings of the 2018 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2018",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

note = "2018 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2018 ; Conference date: 10-06-2018 Through 12-06-2018",

}

Gong, J, He, Y, Ba, A, Liu, YH, Dijkhuis, J, Traferro, S, Bachmann, C, Philips, K & Babaie, M 2018, A 1.33 mW, 1.6ps_rms-integrated-jitter, 1.8-2.7 GHz ring-oscillator-based fractional-n injection-locked DPLL for internet-of-things applications. in AH Hanke & S Turner (eds), Proceedings of the 2018 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2018. vol. 2018-June, 8429041, Institute of Electrical and Electronics Engineers (IEEE), pp. 44-47, 2018 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2018, Philadelphia, United States, 10/06/18. https://doi.org/10.1109/RFIC.2018.8429041

A 1.33 mW, 1.6ps_rms-integrated-jitter, 1.8-2.7 GHz ring-oscillator-based fractional-n injection-locked DPLL for internet-of-things applications. / Gong, Jiang; He, Yuming; Ba, Ao et al.
Proceedings of the 2018 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2018. ed. / Andre Hanke Hanke; Steven Turner. Vol. 2018-June Institute of Electrical and Electronics Engineers (IEEE), 2018. p. 44-47 8429041.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - A 1.33 mW, 1.6psrms-integrated-jitter, 1.8-2.7 GHz ring-oscillator-based fractional-n injection-locked DPLL for internet-of-things applications

AU - Gong, Jiang

AU - He, Yuming

AU - Ba, Ao

AU - Liu, Yao Hong

AU - Dijkhuis, Johan

AU - Traferro, Stefano

AU - Bachmann, Christian

AU - Philips, Kathleen

AU - Babaie, Masoud

PY - 2018

Y1 - 2018

N2 - This paper presents a 1.8-2.7 GHz low-power ring-oscillator-based fractional-N injection-locked digital PLL (IL-DPLL) in 40-nm CMOS for Internet-of-Things clock generation. A two-path injection technique is proposed to improve the in-band phase noise and the integrated jitter of the implemented PLL by 6 dB and 1.8×, respectively. Furthermore, a digital foreground calibration is introduced to effectively reduce reference spurs in a short calibration time of 2 μs. In the worst-case channel, the proposed DPLL using a 64 MHz reference input shows a 1.6 ps integrated jitter, -43.6 dBc reference spur, -45.8 dBc fractional spur and 1 kHz frequency resolution while consuming 1.33 mW power.

AB - This paper presents a 1.8-2.7 GHz low-power ring-oscillator-based fractional-N injection-locked digital PLL (IL-DPLL) in 40-nm CMOS for Internet-of-Things clock generation. A two-path injection technique is proposed to improve the in-band phase noise and the integrated jitter of the implemented PLL by 6 dB and 1.8×, respectively. Furthermore, a digital foreground calibration is introduced to effectively reduce reference spurs in a short calibration time of 2 μs. In the worst-case channel, the proposed DPLL using a 64 MHz reference input shows a 1.6 ps integrated jitter, -43.6 dBc reference spur, -45.8 dBc fractional spur and 1 kHz frequency resolution while consuming 1.33 mW power.

KW - fractional-N DPLL

KW - injection locking

KW - Internet-of-Things

KW - reference spur

KW - ring oscillator

UR - http://www.scopus.com/inward/record.url?scp=85051969542&partnerID=8YFLogxK

U2 - 10.1109/RFIC.2018.8429041

DO - 10.1109/RFIC.2018.8429041

M3 - Conference contribution

AN - SCOPUS:85051969542

SN - 978-153864545-1

VL - 2018-June

SP - 44

EP - 47

BT - Proceedings of the 2018 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2018

A2 - Hanke, Andre Hanke

A2 - Turner, Steven

PB - Institute of Electrical and Electronics Engineers (IEEE)

T2 - 2018 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2018

Y2 - 10 June 2018 through 12 June 2018

ER -

Gong J, He Y, Ba A, Liu YH, Dijkhuis J, Traferro S et al. A 1.33 mW, 1.6ps_rms-integrated-jitter, 1.8-2.7 GHz ring-oscillator-based fractional-n injection-locked DPLL for internet-of-things applications. In Hanke AH, Turner S, editors, Proceedings of the 2018 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2018. Vol. 2018-June. Institute of Electrical and Electronics Engineers (IEEE). 2018. p. 44-47. 8429041 doi: 10.1109/RFIC.2018.8429041