A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS

Peng Chen, Feifei Zhang, Zhirui Zong, Hao Zheng, Teerachot Siriburanon, Bogdan Staszewski

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

8 Citations (Scopus)

Abstract

This paper proposes a power-efficient capacitor-array-based digital-to-time converter (DTC) using a constant-slope approach. Fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate starting supply voltage of the constant slope fed to a fixed threshold comparator. The proposed DTC consumes only 15 μW from a 1V supply, while achieving fine resolution of 103 fs when running at 40 MHz. The measured INL and DNL are 0.73/0.35 LSB within a 5-bit range. The DTC achieves the best figure-of-merit of 8.5 fJ among state-of-the-art when normalizing the product of power and INL to the product of input frequency and range.
Original languageEnglish
Title of host publication2017 IEEE Asian Solid-State Circuits Conference (A-SSCC))
Subtitle of host publicationProceedings of Technical Papers
Place of PublicationDanvers, MA
PublisherIEEE
Pages93-96
Number of pages4
ISBN (Electronic)978-1-5386-3178-2
DOIs
Publication statusPublished - 2017
EventA-SSCC 2017: 13th annual IEEE Asian Solid-State Circuits Conference - Grand Hilton Hotel, Seoul, Korea, Republic of
Duration: 6 Nov 20178 Nov 2017
Conference number: 13
http://www.asscc.org/

Conference

ConferenceA-SSCC 2017
CountryKorea, Republic of
CitySeoul
Period6/11/178/11/17
Internet address

Keywords

  • digital-to-time converter (DTC)
  • low-power
  • low voltage
  • power-efficient
  • capacitor-based DAC (C-DAC)
  • constant slope
  • high resolution
  • INL
  • PLL

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