A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS

Peng Chen; Feifei Zhang; Zhirui Zong; Hao Zheng; Teerachot Siriburanon; Bogdan Staszewski

doi:10.1109/ASSCC.2017.8240224

A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS

Peng Chen, Feifei Zhang, Zhirui Zong, Hao Zheng, Teerachot Siriburanon, Bogdan Staszewski

Electronics

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

13 Citations (Scopus)

Abstract

This paper proposes a power-efficient capacitor-array-based digital-to-time converter (DTC) using a constant-slope approach. Fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate starting supply voltage of the constant slope fed to a fixed threshold comparator. The proposed DTC consumes only 15 μW from a 1V supply, while achieving fine resolution of 103 fs when running at 40 MHz. The measured INL and DNL are 0.73/0.35 LSB within a 5-bit range. The DTC achieves the best figure-of-merit of 8.5 fJ among state-of-the-art when normalizing the product of power and INL to the product of input frequency and range.

Original language	English
Title of host publication	2017 IEEE Asian Solid-State Circuits Conference (A-SSCC))
Subtitle of host publication	Proceedings of Technical Papers
Place of Publication	Danvers, MA
Publisher	IEEE
Pages	93-96
Number of pages	4
ISBN (Electronic)	978-1-5386-3178-2
DOIs	https://doi.org/10.1109/ASSCC.2017.8240224
Publication status	Published - 2017
Event	A-SSCC 2017: 13th annual IEEE Asian Solid-State Circuits Conference - Grand Hilton Hotel, Seoul, Korea, Republic of Duration: 6 Nov 2017 → 8 Nov 2017 Conference number: 13 http://www.asscc.org/

Conference

Conference	A-SSCC 2017
Country/Territory	Korea, Republic of
City	Seoul
Period	6/11/17 → 8/11/17
Internet address	http://www.asscc.org/

Keywords

digital-to-time converter (DTC)
low-power
low voltage
power-efficient
capacitor-based DAC (C-DAC)
constant slope
high resolution
INL
PLL

Access to Document

10.1109/ASSCC.2017.8240224

Cite this

@inproceedings{9a8ded8695ce4d49a64ef1dca5546f47,

title = "A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS",

abstract = "This paper proposes a power-efficient capacitor-array-based digital-to-time converter (DTC) using a constant-slope approach. Fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate starting supply voltage of the constant slope fed to a fixed threshold comparator. The proposed DTC consumes only 15 μW from a 1V supply, while achieving fine resolution of 103 fs when running at 40 MHz. The measured INL and DNL are 0.73/0.35 LSB within a 5-bit range. The DTC achieves the best figure-of-merit of 8.5 fJ among state-of-the-art when normalizing the product of power and INL to the product of input frequency and range.",

keywords = "digital-to-time converter (DTC), low-power, low voltage, power-efficient, capacitor-based DAC (C-DAC), constant slope, high resolution, INL, PLL",

author = "Peng Chen and Feifei Zhang and Zhirui Zong and Hao Zheng and Teerachot Siriburanon and Bogdan Staszewski",

year = "2017",

doi = "10.1109/ASSCC.2017.8240224",

language = "English",

pages = "93--96",

booktitle = "2017 IEEE Asian Solid-State Circuits Conference (A-SSCC))",

publisher = "IEEE",

address = "United States",

note = "A-SSCC 2017 : 13th annual IEEE Asian Solid-State Circuits Conference ; Conference date: 06-11-2017 Through 08-11-2017",

url = "http://www.asscc.org/",

}

Chen, P, Zhang, F, Zong, Z, Zheng, H, Siriburanon, T & Staszewski, B 2017, A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS. in 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)): Proceedings of Technical Papers. IEEE, Danvers, MA, pp. 93-96, A-SSCC 2017, Seoul, Korea, Republic of, 6/11/17. https://doi.org/10.1109/ASSCC.2017.8240224

A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS. / Chen, Peng; Zhang, Feifei; Zong, Zhirui et al.
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)): Proceedings of Technical Papers. Danvers, MA: IEEE, 2017. p. 93-96.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS

AU - Chen, Peng

AU - Zhang, Feifei

AU - Zong, Zhirui

AU - Zheng, Hao

AU - Siriburanon, Teerachot

AU - Staszewski, Bogdan

N1 - Conference code: 13

PY - 2017

Y1 - 2017

N2 - This paper proposes a power-efficient capacitor-array-based digital-to-time converter (DTC) using a constant-slope approach. Fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate starting supply voltage of the constant slope fed to a fixed threshold comparator. The proposed DTC consumes only 15 μW from a 1V supply, while achieving fine resolution of 103 fs when running at 40 MHz. The measured INL and DNL are 0.73/0.35 LSB within a 5-bit range. The DTC achieves the best figure-of-merit of 8.5 fJ among state-of-the-art when normalizing the product of power and INL to the product of input frequency and range.

AB - This paper proposes a power-efficient capacitor-array-based digital-to-time converter (DTC) using a constant-slope approach. Fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate starting supply voltage of the constant slope fed to a fixed threshold comparator. The proposed DTC consumes only 15 μW from a 1V supply, while achieving fine resolution of 103 fs when running at 40 MHz. The measured INL and DNL are 0.73/0.35 LSB within a 5-bit range. The DTC achieves the best figure-of-merit of 8.5 fJ among state-of-the-art when normalizing the product of power and INL to the product of input frequency and range.

KW - digital-to-time converter (DTC)

KW - low-power

KW - low voltage

KW - power-efficient

KW - capacitor-based DAC (C-DAC)

KW - constant slope

KW - high resolution

KW - INL

KW - PLL

U2 - 10.1109/ASSCC.2017.8240224

DO - 10.1109/ASSCC.2017.8240224

M3 - Conference contribution

SP - 93

EP - 96

BT - 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC))

PB - IEEE

CY - Danvers, MA

T2 - A-SSCC 2017

Y2 - 6 November 2017 through 8 November 2017

ER -

A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS

Abstract

Conference

Keywords

Access to Document

Fingerprint

Cite this