Abstract
This paper presents an ultrasound receiver ASIC in 180nm CMOS that enables element-level digitization of echo signals in miniature 3D ultrasound probes. It is the first to integrate an analog front-end and a 10-b Nyquist ADC within the 150 μ m element pitch of a 5-MHz 2D transducer array. To achieve this, a hybrid SAR/shared-single-slope architecture is proposed in which the ramp generator is shared within each 2 × 2 subarray. The ASIC consumes 1.54mW/element and has been successfully demonstrated in an acoustic imaging experiment.
Original language | English |
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Title of host publication | 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers |
Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
Pages | C220-C221 |
Number of pages | 2 |
Volume | 2019-June |
ISBN (Electronic) | 9784863487185 |
DOIs | |
Publication status | Published - 2019 |
Event | 33rd Symposium on VLSI Circuits, VLSI Circuits 2019 - Kyoto, Japan Duration: 9 Jun 2019 → 14 Jun 2019 |
Conference
Conference | 33rd Symposium on VLSI Circuits, VLSI Circuits 2019 |
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Country/Territory | Japan |
City | Kyoto |
Period | 9/06/19 → 14/06/19 |
Keywords
- ADC
- ASIC
- receiver
- ultrasound