A 1.54mW/Element 150μm-Pitch-Matched Receiver ASIC with Element-Level SAR/Shared-Single-Slope Hybrid ADCs for Miniature 3D Ultrasound Probes

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Abstract

This paper presents an ultrasound receiver ASIC in 180nm CMOS that enables element-level digitization of echo signals in miniature 3D ultrasound probes. It is the first to integrate an analog front-end and a 10-b Nyquist ADC within the 150 μ m element pitch of a 5-MHz 2D transducer array. To achieve this, a hybrid SAR/shared-single-slope architecture is proposed in which the ramp generator is shared within each 2 × 2 subarray. The ASIC consumes 1.54mW/element and has been successfully demonstrated in an acoustic imaging experiment.

Original languageEnglish
Title of host publication2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
PagesC220-C221
Number of pages2
Volume2019-June
ISBN (Electronic)9784863487185
DOIs
Publication statusPublished - 2019
Event33rd Symposium on VLSI Circuits, VLSI Circuits 2019 - Kyoto, Japan
Duration: 9 Jun 201914 Jun 2019

Conference

Conference33rd Symposium on VLSI Circuits, VLSI Circuits 2019
CountryJapan
CityKyoto
Period9/06/1914/06/19

Keywords

  • ADC
  • ASIC
  • receiver
  • ultrasound

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    Li, J., Chen, Z., Tan, M., Van Willigen, D., Chen, C., Chang, Z. Y., Noothout, E., De Jong, N., Verweij, M., & Pertijs, M. (2019). A 1.54mW/Element 150μm-Pitch-Matched Receiver ASIC with Element-Level SAR/Shared-Single-Slope Hybrid ADCs for Miniature 3D Ultrasound Probes. In 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers (Vol. 2019-June, pp. C220-C221). [8778200] Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.23919/VLSIC.2019.8778200