A 1.54mW/Element 150μm-Pitch-Matched Receiver ASIC with Element-Level SAR/Shared-Single-Slope Hybrid ADCs for Miniature 3D Ultrasound Probes

Jing Li; Zhao Chen; Mingliang Tan; Douwe Van Willigen; Chao Chen; Zu Yao Chang; Emile Noothout; Nico De Jong; Martin Verweij; Michiel Pertijs

doi:10.23919/VLSIC.2019.8778200

A 1.54mW/Element 150μm-Pitch-Matched Receiver ASIC with Element-Level SAR/Shared-Single-Slope Hybrid ADCs for Miniature 3D Ultrasound Probes

Jing Li, Zhao Chen, Mingliang Tan, Douwe Van Willigen, Chao Chen, Zu Yao Chang, Emile Noothout, Nico De Jong, Martin Verweij, Michiel Pertijs

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

14 Citations (Scopus)

Abstract

This paper presents an ultrasound receiver ASIC in 180nm CMOS that enables element-level digitization of echo signals in miniature 3D ultrasound probes. It is the first to integrate an analog front-end and a 10-b Nyquist ADC within the 150 μ m element pitch of a 5-MHz 2D transducer array. To achieve this, a hybrid SAR/shared-single-slope architecture is proposed in which the ramp generator is shared within each 2 × 2 subarray. The ASIC consumes 1.54mW/element and has been successfully demonstrated in an acoustic imaging experiment.

Original language	English
Title of host publication	2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	C220-C221
Number of pages	2
Volume	2019-June
ISBN (Electronic)	9784863487185
DOIs	https://doi.org/10.23919/VLSIC.2019.8778200
Publication status	Published - 2019
Event	33rd Symposium on VLSI Circuits, VLSI Circuits 2019 - Kyoto, Japan Duration: 9 Jun 2019 → 14 Jun 2019

Conference

Conference	33rd Symposium on VLSI Circuits, VLSI Circuits 2019
Country/Territory	Japan
City	Kyoto
Period	9/06/19 → 14/06/19

Keywords

ADC
ASIC
receiver
ultrasound

Access to Document

10.23919/VLSIC.2019.8778200

Cite this

Li, J., Chen, Z., Tan, M., Van Willigen, D., Chen, C., Chang, Z. Y., Noothout, E., De Jong, N., Verweij, M., & Pertijs, M. (2019). A 1.54mW/Element 150μm-Pitch-Matched Receiver ASIC with Element-Level SAR/Shared-Single-Slope Hybrid ADCs for Miniature 3D Ultrasound Probes. In 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers (Vol. 2019-June, pp. C220-C221). Article 8778200 Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.23919/VLSIC.2019.8778200

@inproceedings{793e2c7e43134c38a9818160be7cd9ce,

title = "A 1.54mW/Element 150μm-Pitch-Matched Receiver ASIC with Element-Level SAR/Shared-Single-Slope Hybrid ADCs for Miniature 3D Ultrasound Probes",

abstract = "This paper presents an ultrasound receiver ASIC in 180nm CMOS that enables element-level digitization of echo signals in miniature 3D ultrasound probes. It is the first to integrate an analog front-end and a 10-b Nyquist ADC within the 150 μ m element pitch of a 5-MHz 2D transducer array. To achieve this, a hybrid SAR/shared-single-slope architecture is proposed in which the ramp generator is shared within each 2 × 2 subarray. The ASIC consumes 1.54mW/element and has been successfully demonstrated in an acoustic imaging experiment.",

keywords = "ADC, ASIC, receiver, ultrasound",

author = "Jing Li and Zhao Chen and Mingliang Tan and {Van Willigen}, Douwe and Chao Chen and Chang, {Zu Yao} and Emile Noothout and {De Jong}, Nico and Martin Verweij and Michiel Pertijs",

year = "2019",

doi = "10.23919/VLSIC.2019.8778200",

language = "English",

volume = "2019-June",

pages = "C220--C221",

booktitle = "2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

note = "33rd Symposium on VLSI Circuits, VLSI Circuits 2019 ; Conference date: 09-06-2019 Through 14-06-2019",

}

Li, J, Chen, Z, Tan, M, Van Willigen, D, Chen, C, Chang, ZY , Noothout, E , De Jong, N , Verweij, M & Pertijs, M 2019, A 1.54mW/Element 150μm-Pitch-Matched Receiver ASIC with Element-Level SAR/Shared-Single-Slope Hybrid ADCs for Miniature 3D Ultrasound Probes. in 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers. vol. 2019-June, 8778200, Institute of Electrical and Electronics Engineers (IEEE), pp. C220-C221, 33rd Symposium on VLSI Circuits, VLSI Circuits 2019, Kyoto, Japan, 9/06/19. https://doi.org/10.23919/VLSIC.2019.8778200

A 1.54mW/Element 150μm-Pitch-Matched Receiver ASIC with Element-Level SAR/Shared-Single-Slope Hybrid ADCs for Miniature 3D Ultrasound Probes. / Li, Jing; Chen, Zhao; Tan, Mingliang et al.
2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers. Vol. 2019-June Institute of Electrical and Electronics Engineers (IEEE), 2019. p. C220-C221 8778200.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - A 1.54mW/Element 150μm-Pitch-Matched Receiver ASIC with Element-Level SAR/Shared-Single-Slope Hybrid ADCs for Miniature 3D Ultrasound Probes

AU - Li, Jing

AU - Chen, Zhao

AU - Tan, Mingliang

AU - Van Willigen, Douwe

AU - Chen, Chao

AU - Chang, Zu Yao

AU - Noothout, Emile

AU - De Jong, Nico

AU - Verweij, Martin

AU - Pertijs, Michiel

PY - 2019

Y1 - 2019

N2 - This paper presents an ultrasound receiver ASIC in 180nm CMOS that enables element-level digitization of echo signals in miniature 3D ultrasound probes. It is the first to integrate an analog front-end and a 10-b Nyquist ADC within the 150 μ m element pitch of a 5-MHz 2D transducer array. To achieve this, a hybrid SAR/shared-single-slope architecture is proposed in which the ramp generator is shared within each 2 × 2 subarray. The ASIC consumes 1.54mW/element and has been successfully demonstrated in an acoustic imaging experiment.

AB - This paper presents an ultrasound receiver ASIC in 180nm CMOS that enables element-level digitization of echo signals in miniature 3D ultrasound probes. It is the first to integrate an analog front-end and a 10-b Nyquist ADC within the 150 μ m element pitch of a 5-MHz 2D transducer array. To achieve this, a hybrid SAR/shared-single-slope architecture is proposed in which the ramp generator is shared within each 2 × 2 subarray. The ASIC consumes 1.54mW/element and has been successfully demonstrated in an acoustic imaging experiment.

KW - ADC

KW - ASIC

KW - receiver

KW - ultrasound

UR - http://www.scopus.com/inward/record.url?scp=85073906566&partnerID=8YFLogxK

U2 - 10.23919/VLSIC.2019.8778200

DO - 10.23919/VLSIC.2019.8778200

M3 - Conference contribution

AN - SCOPUS:85073906566

VL - 2019-June

SP - C220-C221

BT - 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers

PB - Institute of Electrical and Electronics Engineers (IEEE)

T2 - 33rd Symposium on VLSI Circuits, VLSI Circuits 2019

Y2 - 9 June 2019 through 14 June 2019

ER -

Li J, Chen Z, Tan M, Van Willigen D, Chen C, Chang ZY et al. A 1.54mW/Element 150μm-Pitch-Matched Receiver ASIC with Element-Level SAR/Shared-Single-Slope Hybrid ADCs for Miniature 3D Ultrasound Probes. In 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers. Vol. 2019-June. Institute of Electrical and Electronics Engineers (IEEE). 2019. p. C220-C221. 8778200 doi: 10.23919/VLSIC.2019.8778200

A 1.54mW/Element 150μm-Pitch-Matched Receiver ASIC with Element-Level SAR/Shared-Single-Slope Hybrid ADCs for Miniature 3D Ultrasound Probes

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