@inproceedings{7b809b6a594f4603aac22f0a60be2027,
title = "A 1.8 V 3.2 /spl mu/W comparator for use in a CMOS imager column-level single-slope ADC",
abstract = "In this paper, a 1.8 V 3.2 /spl mu/W comparator is presented. It features a hybrid offset compensation scheme and achieves over 60 dB gain with an input offset below 150 /spl mu/V. The comparator is designed in a 0.18 /spl mu/m CMOS process and is specifically designed to be used as the key component of a column-level single-slope ADC of a CMOS imager. This ADC architecture is attractive because of its low noise, but so far this has come at the price of a relatively high power consumption. Using this comparator design, the power consumption of column-level single-slope ADC can be reduced significantly.",
keywords = "conference contrib. refereed, Conf.proc. > 3 pag",
author = "MF Snoeij and AJP Theuwissen and JH Huijsing",
note = "Editor onbekend, WPM; ISCAS 2005 : IEEE international symposium on circuits and systems ; Conference date: 23-05-2005 Through 26-05-2005",
year = "2005",
doi = "10.1109/ISCAS.2005.1466047",
language = "English",
publisher = "IEEE Society",
pages = "6162--6165",
booktitle = "ISCAS 2005, IEEE International Symposium on Circuits and Systems, 2005",
}