A 1.8 V 3.2 /spl mu/W comparator for use in a CMOS imager column-level single-slope ADC

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

23 Citations (Scopus)

Abstract

In this paper, a 1.8 V 3.2 /spl mu/W comparator is presented. It features a hybrid offset compensation scheme and achieves over 60 dB gain with an input offset below 150 /spl mu/V. The comparator is designed in a 0.18 /spl mu/m CMOS process and is specifically designed to be used as the key component of a column-level single-slope ADC of a CMOS imager. This ADC architecture is attractive because of its low noise, but so far this has come at the price of a relatively high power consumption. Using this comparator design, the power consumption of column-level single-slope ADC can be reduced significantly.
Original languageEnglish
Title of host publicationISCAS 2005, IEEE International Symposium on Circuits and Systems, 2005
Place of PublicationStefanidge, UK
PublisherIEEE Society
Pages6162-6165
Number of pages4
DOIs
Publication statusPublished - 2005
EventISCAS 2005: IEEE international symposium on circuits and systems - Kobe, Japan
Duration: 23 May 200526 May 2005

Publication series

Name
Volume6

Conference

ConferenceISCAS 2005
Country/TerritoryJapan
CityKobe
Period23/05/0526/05/05

Bibliographical note

Editor onbekend, WPM

Keywords

  • conference contrib. refereed
  • Conf.proc. > 3 pag

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