A 2 GHz 0.98 mW 4-bit SAR-Based Quantizer with ELD Compensation in an UWB CT ΣΔ Modulator

M. Zhou; M. Neofytou; M. Bolatkale; Q. Liu; C. Zhang; P. Cenci; G. Radulov; P. Baltus; L. Breems

doi:10.1109/ISCAS.2018.8350889

A 2 GHz 0.98 mW 4-bit SAR-Based Quantizer with ELD Compensation in an UWB CT ΣΔ Modulator

M. Zhou, M. Neofytou, M. Bolatkale, Q. Liu, C. Zhang, P. Cenci, G. Radulov, P. Baltus, L. Breems

Electronic Instrumentation

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

Abstract

This paper presents a 2 GHz 4-bit asynchronous successive approximation register (SAR) quantizer to enable an ultra-wideband continuous-time (CT) sigma-delta modulator (SDM). Low latency is required for the stability of the SDM. The excess-loop-delay compensation (ELDC) is embedded in the SAR quantizer by adding an extra switched-capacitor DAC segment with two separate reference voltages. To achieve high speed, a g_m-boosted StrongARM latch and the monotonic switching scheme are used. This paper presents the transistor-level circuit implementation and the complete verification of the CT SDM. Simulation results show the power consumption of this SAR-based quantizer including ELDC is 0.98 mW, leading to a very competitive Figure-of-Merit of 30.6 fJ/conv.-step.

Original language	English
Title of host publication	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
Publisher	IEEE
Number of pages	5
ISBN (Electronic)	9781538648810
DOIs	https://doi.org/10.1109/ISCAS.2018.8350889
Publication status	Published - 2018
Event	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence, Italy Duration: 27 May 2018 → 30 May 2018

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2018-May
ISSN (Print)	0271-4310

Conference

Conference	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
Country/Territory	Italy
City	Florence
Period	27/05/18 → 30/05/18

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10.1109/ISCAS.2018.8350889

Cite this

Zhou, M., Neofytou, M., Bolatkale, M., Liu, Q., Zhang, C., Cenci, P., Radulov, G., Baltus, P., & Breems, L. (2018). A 2 GHz 0.98 mW 4-bit SAR-Based Quantizer with ELD Compensation in an UWB CT ΣΔ Modulator. In 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings Article 8350889 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2018-May). IEEE. https://doi.org/10.1109/ISCAS.2018.8350889

@inproceedings{d0fbaa61452c491cad468fcffe728f37,

title = "A 2 GHz 0.98 mW 4-bit SAR-Based Quantizer with ELD Compensation in an UWB CT ΣΔ Modulator",

abstract = "This paper presents a 2 GHz 4-bit asynchronous successive approximation register (SAR) quantizer to enable an ultra-wideband continuous-time (CT) sigma-delta modulator (SDM). Low latency is required for the stability of the SDM. The excess-loop-delay compensation (ELDC) is embedded in the SAR quantizer by adding an extra switched-capacitor DAC segment with two separate reference voltages. To achieve high speed, a gm-boosted StrongARM latch and the monotonic switching scheme are used. This paper presents the transistor-level circuit implementation and the complete verification of the CT SDM. Simulation results show the power consumption of this SAR-based quantizer including ELDC is 0.98 mW, leading to a very competitive Figure-of-Merit of 30.6 fJ/conv.-step.",

author = "M. Zhou and M. Neofytou and M. Bolatkale and Q. Liu and C. Zhang and P. Cenci and G. Radulov and P. Baltus and L. Breems",

year = "2018",

doi = "10.1109/ISCAS.2018.8350889",

language = "English",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "IEEE",

booktitle = "2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings",

address = "United States",

note = "2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 ; Conference date: 27-05-2018 Through 30-05-2018",

}

Zhou, M, Neofytou, M, Bolatkale, M, Liu, Q, Zhang, C, Cenci, P, Radulov, G, Baltus, P & Breems, L 2018, A 2 GHz 0.98 mW 4-bit SAR-Based Quantizer with ELD Compensation in an UWB CT ΣΔ Modulator. in 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings., 8350889, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2018-May, IEEE, 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018, Florence, Italy, 27/05/18. https://doi.org/10.1109/ISCAS.2018.8350889

A 2 GHz 0.98 mW 4-bit SAR-Based Quantizer with ELD Compensation in an UWB CT ΣΔ Modulator. / Zhou, M.; Neofytou, M.; Bolatkale, M. et al.
2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. IEEE, 2018. 8350889 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2018-May).

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

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T1 - A 2 GHz 0.98 mW 4-bit SAR-Based Quantizer with ELD Compensation in an UWB CT ΣΔ Modulator

AU - Zhou, M.

AU - Neofytou, M.

AU - Bolatkale, M.

AU - Liu, Q.

AU - Zhang, C.

AU - Cenci, P.

AU - Radulov, G.

AU - Baltus, P.

AU - Breems, L.

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N2 - This paper presents a 2 GHz 4-bit asynchronous successive approximation register (SAR) quantizer to enable an ultra-wideband continuous-time (CT) sigma-delta modulator (SDM). Low latency is required for the stability of the SDM. The excess-loop-delay compensation (ELDC) is embedded in the SAR quantizer by adding an extra switched-capacitor DAC segment with two separate reference voltages. To achieve high speed, a gm-boosted StrongARM latch and the monotonic switching scheme are used. This paper presents the transistor-level circuit implementation and the complete verification of the CT SDM. Simulation results show the power consumption of this SAR-based quantizer including ELDC is 0.98 mW, leading to a very competitive Figure-of-Merit of 30.6 fJ/conv.-step.

AB - This paper presents a 2 GHz 4-bit asynchronous successive approximation register (SAR) quantizer to enable an ultra-wideband continuous-time (CT) sigma-delta modulator (SDM). Low latency is required for the stability of the SDM. The excess-loop-delay compensation (ELDC) is embedded in the SAR quantizer by adding an extra switched-capacitor DAC segment with two separate reference voltages. To achieve high speed, a gm-boosted StrongARM latch and the monotonic switching scheme are used. This paper presents the transistor-level circuit implementation and the complete verification of the CT SDM. Simulation results show the power consumption of this SAR-based quantizer including ELDC is 0.98 mW, leading to a very competitive Figure-of-Merit of 30.6 fJ/conv.-step.

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A 2 GHz 0.98 mW 4-bit SAR-Based Quantizer with ELD Compensation in an UWB CT ΣΔ Modulator

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