A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology

Zhongkai Wang*, Minsoo Choi, Paul Kwon, Kyoungtae Lee, Bozhi Yin, Zhaokai Liu, Kwanseo Park, Ayan Biswas, Sijun Du, More Authors

*Corresponding author for this work

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Abstract

This paper presents a complete 200Gb/s PAM-4 transmitter (TX) in 28nm CMOS technology. The transmitter features a hybrid sub-sampling PLL (SSPLL) with a delta-sigma (?S) modulator, clock distribution network with flexible timing control, and data path with a hybrid 5-tap Feed-Forward Equalizer (FFE) and T-coil for bandwidth extension. The prototype chip achieves 4.69 pJ/bit efficiency, 54mV eye height, 0.27UI eye width, and 97% RLM under -6dB channel loss at 50GHz.

Original languageEnglish
Title of host publication2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages34-35
Number of pages2
ISBN (Electronic)978-1-6654-9772-5
DOIs
Publication statusPublished - 2022
Event2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 - Honolulu, United States
Duration: 12 Jun 202217 Jun 2022

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2022-June
ISSN (Print)0743-1562

Conference

Conference2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Country/TerritoryUnited States
CityHonolulu
Period12/06/2217/06/22

Keywords

  • 28nm
  • CMOS
  • SerDes
  • Sub-sampling PLL
  • Transmitter

Fingerprint

Dive into the research topics of 'A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology'. Together they form a unique fingerprint.

Cite this