This paper presents a complete 200Gb/s PAM-4 transmitter (TX) in 28nm CMOS technology. The transmitter features a hybrid sub-sampling PLL (SSPLL) with a delta-sigma (?S) modulator, clock distribution network with flexible timing control, and data path with a hybrid 5-tap Feed-Forward Equalizer (FFE) and T-coil for bandwidth extension. The prototype chip achieves 4.69 pJ/bit efficiency, 54mV eye height, 0.27UI eye width, and 97% RLM under -6dB channel loss at 50GHz.
|Title of host publication||2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Number of pages||2|
|Publication status||Published - 2022|
|Event||2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 - Honolulu, United States|
Duration: 12 Jun 2022 → 17 Jun 2022
|Name||Digest of Technical Papers - Symposium on VLSI Technology|
|Conference||2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022|
|Period||12/06/22 → 17/06/22|
Bibliographical noteGreen Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care
Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.
- Sub-sampling PLL