A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology

Zhongkai Wang; Minsoo Choi; Paul Kwon; Kyoungtae Lee; Bozhi Yin; Zhaokai Liu; Kwanseo Park; Ayan Biswas; Sijun Du; More Authors

doi:10.1109/VLSITechnologyandCir46769.2022.9830237

A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology

Zhongkai Wang^*
, Minsoo Choi
, Paul Kwon
, Kyoungtae Lee
, Bozhi Yin
, Zhaokai Liu
, Kwanseo Park
, Ayan Biswas
, Sijun Du
, More Authors

^*Corresponding author for this work

Electronic Instrumentation

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

4 Citations (Scopus)

423 Downloads (Pure)

Abstract

This paper presents a complete 200Gb/s PAM-4 transmitter (TX) in 28nm CMOS technology. The transmitter features a hybrid sub-sampling PLL (SSPLL) with a delta-sigma (?S) modulator, clock distribution network with flexible timing control, and data path with a hybrid 5-tap Feed-Forward Equalizer (FFE) and T-coil for bandwidth extension. The prototype chip achieves 4.69 pJ/bit efficiency, 54mV eye height, 0.27UI eye width, and 97% RLM under -6dB channel loss at 50GHz.

Original language	English
Title of host publication	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Publisher	IEEE
Pages	34-35
Number of pages	2
ISBN (Electronic)	978-1-6654-9772-5
DOIs	https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830237
Publication status	Published - 2022
Event	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 - Honolulu, United States Duration: 12 Jun 2022 → 17 Jun 2022

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2022-June
ISSN (Print)	0743-1562

Conference

Conference	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Country/Territory	United States
City	Honolulu
Period	12/06/22 → 17/06/22

Bibliographical note

Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care
Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

Keywords

28nm
CMOS
SerDes
Sub-sampling PLL
Transmitter

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10.1109/VLSITechnologyandCir46769.2022.9830237

A_200Gb_s_PAM-4_Transmitter_with_Hybrid_Sub-Sampling_PLL_in_28nm_CMOS_TechnologyFinal published version, 1.3 MB

Cite this

Wang, Z., Choi, M., Kwon, P., Lee, K., Yin, B., Liu, Z., Park, K., Biswas, A., Du, S., & More Authors (2022). A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology. In 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 (pp. 34-35). (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2022-June). IEEE. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830237

@inproceedings{e438cca0245c4bb08f5b4055b186752b,

title = "A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology",

abstract = "This paper presents a complete 200Gb/s PAM-4 transmitter (TX) in 28nm CMOS technology. The transmitter features a hybrid sub-sampling PLL (SSPLL) with a delta-sigma (?S) modulator, clock distribution network with flexible timing control, and data path with a hybrid 5-tap Feed-Forward Equalizer (FFE) and T-coil for bandwidth extension. The prototype chip achieves 4.69 pJ/bit efficiency, 54mV eye height, 0.27UI eye width, and 97\% RLM under -6dB channel loss at 50GHz. ",

keywords = "28nm, CMOS, SerDes, Sub-sampling PLL, Transmitter",

author = "Zhongkai Wang and Minsoo Choi and Paul Kwon and Kyoungtae Lee and Bozhi Yin and Zhaokai Liu and Kwanseo Park and Ayan Biswas and Sijun Du and \{More Authors\}",

note = "Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.; 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 ; Conference date: 12-06-2022 Through 17-06-2022",

year = "2022",

doi = "10.1109/VLSITechnologyandCir46769.2022.9830237",

language = "English",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

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pages = "34--35",

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address = "United States",

}

Wang, Z, Choi, M, Kwon, P, Lee, K, Yin, B, Liu, Z, Park, K, Biswas, A, Du, S & More Authors 2022, A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology. in 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Digest of Technical Papers - Symposium on VLSI Technology, vol. 2022-June, IEEE, pp. 34-35, 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022, Honolulu, United States, 12/06/22. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830237

A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology. / Wang, Zhongkai; Choi, Minsoo; Kwon, Paul et al.
2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. IEEE, 2022. p. 34-35 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2022-June).

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

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AU - Wang, Zhongkai

AU - Choi, Minsoo

AU - Kwon, Paul

AU - Lee, Kyoungtae

AU - Yin, Bozhi

AU - Liu, Zhaokai

AU - Park, Kwanseo

AU - Biswas, Ayan

AU - Du, Sijun

AU - More Authors, null

N1 - Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

PY - 2022

Y1 - 2022

N2 - This paper presents a complete 200Gb/s PAM-4 transmitter (TX) in 28nm CMOS technology. The transmitter features a hybrid sub-sampling PLL (SSPLL) with a delta-sigma (?S) modulator, clock distribution network with flexible timing control, and data path with a hybrid 5-tap Feed-Forward Equalizer (FFE) and T-coil for bandwidth extension. The prototype chip achieves 4.69 pJ/bit efficiency, 54mV eye height, 0.27UI eye width, and 97% RLM under -6dB channel loss at 50GHz.

AB - This paper presents a complete 200Gb/s PAM-4 transmitter (TX) in 28nm CMOS technology. The transmitter features a hybrid sub-sampling PLL (SSPLL) with a delta-sigma (?S) modulator, clock distribution network with flexible timing control, and data path with a hybrid 5-tap Feed-Forward Equalizer (FFE) and T-coil for bandwidth extension. The prototype chip achieves 4.69 pJ/bit efficiency, 54mV eye height, 0.27UI eye width, and 97% RLM under -6dB channel loss at 50GHz.

KW - 28nm

KW - CMOS

KW - SerDes

KW - Sub-sampling PLL

KW - Transmitter

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DO - 10.1109/VLSITechnologyandCir46769.2022.9830237

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SP - 34

EP - 35

BT - 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022

PB - IEEE

T2 - 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022

Y2 - 12 June 2022 through 17 June 2022

ER -

A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology

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Bibliographical note

Keywords

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