A 2.1 M pixels, 120 frame/s CMOS image sensor with column-parallel ¿¿ ADC Architecture

Y Chae, J Cheon, S Lim, M Kwon, K Yoo, W Jung, D.H Lee, S Ham, G Han

Research output: Contribution to journalArticleScientificpeer-review

130 Citations (Scopus)
Original languageEnglish
Pages (from-to)236-247
Number of pages12
JournalIEEE Journal of Solid State Circuits
Volume46
Issue number1
DOIs
Publication statusPublished - 2011

Cite this

Chae, Y., Cheon, J., Lim, S., Kwon, M., Yoo, K., Jung, W., Lee, D. H., Ham, S., & Han, G. (2011). A 2.1 M pixels, 120 frame/s CMOS image sensor with column-parallel ¿¿ ADC Architecture. IEEE Journal of Solid State Circuits, 46(1), 236-247. https://doi.org/10.1109/JSSC.2010.2085910