A 252 × 144 SPAD Pixel Flash Lidar with 1728 Dual-Clock 48.8 PS TDCs, Integrated Histogramming and 14.9-to-1 Compression in 180NM CMOS Technology

Scott Lindner, Chao Zhang, Ivan Michel Antolovic, Martin Wolf, Edoardo Charbon

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

20 Citations (Scopus)

Abstract

A 252 × 144 single-photon avalanche diode (SPAD) pixel FLASH LiDAR is implemented in 180nm CMOS with 28.5μm pixel pitch and 28% fill factor. The sensor includes a collision detection bus with dynamic reallocation of 48.8 ps dual-clock time-to-digital converters (TDCs). It can operate in time-correlated single-photon counting (TCSPC), single-photon counting (SPC), peak-detection (PD) and partial-histogramming (PH) modes. The PD and PH modes are enabled by the first implementation of integrated histogramming for a full array via an SRAM based partial histogramming readout (PHR) scheme. This provides 16 5-bit bins for each pixel to enable a 14.9-to-l compression ratio.

Original languageEnglish
Title of host publication2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
EditorsH.S. Philip Wong
Place of PublicationPiscataway, NJ
PublisherIEEE
Pages69-70
Number of pages2
Volume2018-June
ISBN (Electronic)978-153866700-2
DOIs
Publication statusPublished - 2018
Event2018 Symposia on VLSI Technology and Circuits: 2018 VLSI Technology Symposium - 2018 VLSI Circuits - Hilton Hawaiian Village, Honolulu, United States
Duration: 18 Jun 201822 Jun 2018

Conference

Conference2018 Symposia on VLSI Technology and Circuits
CountryUnited States
CityHonolulu
Period18/06/1822/06/18

Keywords

  • CMOS
  • Histogramming
  • LiDAR
  • SPAD
  • TCSPC

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