Abstract
A 252 × 144 single-photon avalanche diode (SPAD) pixel FLASH LiDAR is implemented in 180nm CMOS with 28.5μm pixel pitch and 28% fill factor. The sensor includes a collision detection bus with dynamic reallocation of 48.8 ps dual-clock time-to-digital converters (TDCs). It can operate in time-correlated single-photon counting (TCSPC), single-photon counting (SPC), peak-detection (PD) and partial-histogramming (PH) modes. The PD and PH modes are enabled by the first implementation of integrated histogramming for a full array via an SRAM based partial histogramming readout (PHR) scheme. This provides 16 5-bit bins for each pixel to enable a 14.9-to-l compression ratio.
Original language | English |
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Title of host publication | 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 |
Editors | H.S. Philip Wong |
Place of Publication | Piscataway, NJ |
Publisher | IEEE |
Pages | 69-70 |
Number of pages | 2 |
Volume | 2018-June |
ISBN (Electronic) | 978-153866700-2 |
DOIs | |
Publication status | Published - 2018 |
Event | 2018 Symposia on VLSI Technology and Circuits: 2018 VLSI Technology Symposium - 2018 VLSI Circuits - Hilton Hawaiian Village, Honolulu, United States Duration: 18 Jun 2018 → 22 Jun 2018 |
Conference
Conference | 2018 Symposia on VLSI Technology and Circuits |
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Country/Territory | United States |
City | Honolulu |
Period | 18/06/18 → 22/06/18 |
Keywords
- CMOS
- Histogramming
- LiDAR
- SPAD
- TCSPC