A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Abstract

In a fractional-N PLL, it is beneficial to minimize the input range of its phase detector (PD) as it promotes better linearity and higher PD gain for suppressing noise contributions of the following loop components. This can be done by canceling the predicted instantaneous time offset between the frequency reference (FREF) and the variable oscillator-clock (CKV) edges prior to the PD. There are currently two main cancellation strategies. The first is to align FREF and CKV by inserting a digital-to-time converter (DTC) on either path. However, due to the DTC nonlinearity and its susceptibility to PVT variations, the PLL can suffer from large fractional spurs. Although system-level techniques, e.g., background calibration [1], supply ripple reduction [2], and DTC code randomization [3], can partially alleviate these DTC issues, the overall system complexity worsens. The second method is to convert and cancel the predicted time offset in the voltage domain [4]. This arrangement is less sensitive to PVT variations. However, the accuracy of the time-to-voltage conversion relies on the strict trade-offs between the power consumption, noise, and linearity of a current source. In this work, we introduce a third solution based on a time-mode arithmetic unit (TAU), which outputs a weighted sum of time delays between the (falling) edges of FREF and CKV, as well as between two consecutive CKV edges. Compared with DTC-based solutions, it is less sensitive to PVT variations, as its output merely varies by the ratio of RC time constants, thus ensuring low fractional spurs with no extra system complexity. Compared to the voltage-domain solutions, the absence of a current source is beneficial for phase-noise optimization and migration to more advanced technology nodes. Moreover, TAU can implicitly provide a time-amplification (TA) gain, thus further suppressing the noise of subsequent blocks.
Original languageEnglish
Title of host publication2022 IEEE International Solid-State Circuits Conference, ISSCC 2022
Subtitle of host publicationDigest of technical papers
EditorsLaura C. Fujino
Place of PublicationDanvers
PublisherIEEE
Pages380-382
Number of pages3
ISBN (Electronic)978-1-6654-2800-2
ISBN (Print)978-1-6654-2801-9
DOIs
Publication statusPublished - 2022
Event2022 IEEE International Solid- State Circuits Conference (ISSCC) - Online at San Francisco, United States
Duration: 20 Feb 202226 Feb 2022

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume2022-February
ISSN (Print)0193-6530

Conference

Conference2022 IEEE International Solid- State Circuits Conference (ISSCC)
Abbreviated titleISSCC 2022
Country/TerritoryUnited States
CityOnline at San Francisco
Period20/02/2226/02/22

Fingerprint

Dive into the research topics of 'A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs'. Together they form a unique fingerprint.

Cite this