A 28 nm 2 GS/s 5-b single-channel SAR ADC with gm-boosted StrongARM comparator

Pierluigi Cenci, Muhammed Bolatkale, Robert Rutten, Gerard Lassche, Kofi Makinwa, Lucien Breems

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

4 Citations (Scopus)

Abstract

This paper presents a 2 GS/s 5-b single-channel SAR ADC in 28 nm CMOS. The ADC uses a gm-boosted StrongARM comparator to achieve the highest reported sampling frequency for a non-time-interleaved SAR ADC. Its high sampling frequency, large input signal capability and one clock cycle latency make the ADC suitable for time-interleaved, multi-stage and feedback ADC architectures. The ADC occupies 900 μm2 and consumes 1.25 mW from a 0.9 V supply. Without calibration, and when operated at 1.5 GS/s it achieves 30.3 dB SNDR (FOMw=31.2 fJ/conv.-step). This drops slightly, to 27.4dB, at the maximum sampling rate of 2 GS/s.
Original languageEnglish
Title of host publication43rd IEEE European Solid-State Circuits Conference (ESSCIRC 2017)
Place of PublicationPiscataway, NJ
PublisherIEEE
Pages171-174
Number of pages4
ISBN (Electronic)978-1-5090-5025-3
DOIs
Publication statusPublished - 2017
EventESSDERC-ESSCIRC 2017: 47th European Solid-State Device Research Conference - 43rd European Solid-State Circuits Conference - Leuven, Belgium
Duration: 11 Sep 201714 Sep 2017
https://www.esscirc-essderc2017.org/

Conference

ConferenceESSDERC-ESSCIRC 2017
CountryBelgium
CityLeuven
Period11/09/1714/09/17
Internet address

Keywords

  • SAR converter
  • Single-channel
  • rail-to-rail input signal
  • asynchronous logic
  • bottom plate sampling
  • 28 nm CMOS
  • gm-boosted StrongARM comparator

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  • Cite this

    Cenci, P., Bolatkale, M., Rutten, R., Lassche, G., Makinwa, K., & Breems, L. (2017). A 28 nm 2 GS/s 5-b single-channel SAR ADC with gm-boosted StrongARM comparator. In 43rd IEEE European Solid-State Circuits Conference (ESSCIRC 2017) (pp. 171-174). IEEE. https://doi.org/10.1109/ESSCIRC.2017.8094553