A 28 nm 2 GS/s 5-b single-channel SAR ADC with gm-boosted StrongARM comparator

Pierluigi Cenci; Muhammed Bolatkale; Robert Rutten; Gerard Lassche; Kofi Makinwa; Lucien Breems

doi:10.1109/ESSCIRC.2017.8094553

A 28 nm 2 GS/s 5-b single-channel SAR ADC with gm-boosted StrongARM comparator

Pierluigi Cenci, Muhammed Bolatkale, Robert Rutten, Gerard Lassche, Kofi Makinwa, Lucien Breems

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

10 Citations (Scopus)

Abstract

This paper presents a 2 GS/s 5-b single-channel SAR ADC in 28 nm CMOS. The ADC uses a gm-boosted StrongARM comparator to achieve the highest reported sampling frequency for a non-time-interleaved SAR ADC. Its high sampling frequency, large input signal capability and one clock cycle latency make the ADC suitable for time-interleaved, multi-stage and feedback ADC architectures. The ADC occupies 900 μm2 and consumes 1.25 mW from a 0.9 V supply. Without calibration, and when operated at 1.5 GS/s it achieves 30.3 dB SNDR (FOMw=31.2 fJ/conv.-step). This drops slightly, to 27.4dB, at the maximum sampling rate of 2 GS/s.

Original language	English
Title of host publication	43rd IEEE European Solid-State Circuits Conference (ESSCIRC 2017)
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	171-174
Number of pages	4
ISBN (Electronic)	978-1-5090-5025-3
DOIs	https://doi.org/10.1109/ESSCIRC.2017.8094553
Publication status	Published - 2017
Event	ESSDERC-ESSCIRC 2017: 47th European Solid-State Device Research Conference - 43rd European Solid-State Circuits Conference - Leuven, Belgium Duration: 11 Sept 2017 → 14 Sept 2017 https://www.esscirc-essderc2017.org/

Conference

Conference	ESSDERC-ESSCIRC 2017
Country/Territory	Belgium
City	Leuven
Period	11/09/17 → 14/09/17
Internet address	https://www.esscirc-essderc2017.org/

Keywords

SAR converter
Single-channel
rail-to-rail input signal
asynchronous logic
bottom plate sampling
28 nm CMOS
gm-boosted StrongARM comparator

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10.1109/ESSCIRC.2017.8094553

Cite this

@inproceedings{8bbc1c41b4c6499ab69790b783206c4c,

title = "A 28 nm 2 GS/s 5-b single-channel SAR ADC with gm-boosted StrongARM comparator",

abstract = "This paper presents a 2 GS/s 5-b single-channel SAR ADC in 28 nm CMOS. The ADC uses a gm-boosted StrongARM comparator to achieve the highest reported sampling frequency for a non-time-interleaved SAR ADC. Its high sampling frequency, large input signal capability and one clock cycle latency make the ADC suitable for time-interleaved, multi-stage and feedback ADC architectures. The ADC occupies 900 μm2 and consumes 1.25 mW from a 0.9 V supply. Without calibration, and when operated at 1.5 GS/s it achieves 30.3 dB SNDR (FOMw=31.2 fJ/conv.-step). This drops slightly, to 27.4dB, at the maximum sampling rate of 2 GS/s.",

keywords = "SAR converter, Single-channel, rail-to-rail input signal, asynchronous logic, bottom plate sampling, 28 nm CMOS, gm-boosted StrongARM comparator",

author = "Pierluigi Cenci and Muhammed Bolatkale and Robert Rutten and Gerard Lassche and Kofi Makinwa and Lucien Breems",

year = "2017",

doi = "10.1109/ESSCIRC.2017.8094553",

language = "English",

pages = "171--174",

booktitle = "43rd IEEE European Solid-State Circuits Conference (ESSCIRC 2017)",

publisher = "IEEE",

address = "United States",

note = "ESSDERC-ESSCIRC 2017 : 47th European Solid-State Device Research Conference - 43rd European Solid-State Circuits Conference ; Conference date: 11-09-2017 Through 14-09-2017",

url = "https://www.esscirc-essderc2017.org/",

}

A 28 nm 2 GS/s 5-b single-channel SAR ADC with gm-boosted StrongARM comparator. / Cenci, Pierluigi; Bolatkale, Muhammed; Rutten, Robert et al.
43rd IEEE European Solid-State Circuits Conference (ESSCIRC 2017). Piscataway, NJ: IEEE, 2017. p. 171-174.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - A 28 nm 2 GS/s 5-b single-channel SAR ADC with gm-boosted StrongARM comparator

AU - Cenci, Pierluigi

AU - Bolatkale, Muhammed

AU - Rutten, Robert

AU - Lassche, Gerard

AU - Makinwa, Kofi

AU - Breems, Lucien

PY - 2017

Y1 - 2017

N2 - This paper presents a 2 GS/s 5-b single-channel SAR ADC in 28 nm CMOS. The ADC uses a gm-boosted StrongARM comparator to achieve the highest reported sampling frequency for a non-time-interleaved SAR ADC. Its high sampling frequency, large input signal capability and one clock cycle latency make the ADC suitable for time-interleaved, multi-stage and feedback ADC architectures. The ADC occupies 900 μm2 and consumes 1.25 mW from a 0.9 V supply. Without calibration, and when operated at 1.5 GS/s it achieves 30.3 dB SNDR (FOMw=31.2 fJ/conv.-step). This drops slightly, to 27.4dB, at the maximum sampling rate of 2 GS/s.

AB - This paper presents a 2 GS/s 5-b single-channel SAR ADC in 28 nm CMOS. The ADC uses a gm-boosted StrongARM comparator to achieve the highest reported sampling frequency for a non-time-interleaved SAR ADC. Its high sampling frequency, large input signal capability and one clock cycle latency make the ADC suitable for time-interleaved, multi-stage and feedback ADC architectures. The ADC occupies 900 μm2 and consumes 1.25 mW from a 0.9 V supply. Without calibration, and when operated at 1.5 GS/s it achieves 30.3 dB SNDR (FOMw=31.2 fJ/conv.-step). This drops slightly, to 27.4dB, at the maximum sampling rate of 2 GS/s.

KW - SAR converter

KW - Single-channel

KW - rail-to-rail input signal

KW - asynchronous logic

KW - bottom plate sampling

KW - 28 nm CMOS

KW - gm-boosted StrongARM comparator

U2 - 10.1109/ESSCIRC.2017.8094553

DO - 10.1109/ESSCIRC.2017.8094553

M3 - Conference contribution

SP - 171

EP - 174

BT - 43rd IEEE European Solid-State Circuits Conference (ESSCIRC 2017)

PB - IEEE

CY - Piscataway, NJ

T2 - ESSDERC-ESSCIRC 2017

Y2 - 11 September 2017 through 14 September 2017

ER -

A 28 nm 2 GS/s 5-b single-channel SAR ADC with gm-boosted StrongARM comparator

Abstract

Conference

Keywords

Access to Document

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Cite this