A 280 μW Dynamic Zoom ADC With 120 dB DR 118 dB SNDR in 1 kHz BW

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Abstract

This paper presents a dynamic zoom analog-to-digital converter for use in low-bandwidth (<1 kHz) instrumentation applications. It employs a high-speed asynchronous successive approximation register (SAR) ADC that dynamically updates the references of a fully differential Δ Σ ADC. Compared to previous zoom ADCs, faster reference updates relax the loop filter requirements, thus allowing the adoption of energy-efficient amplifiers. Fabricated in a 0.16-μm CMOS process, the prototype occupies 0.26 mm² and achieves 119.1-dB peak signal-to-noise ratio (SNR), 118.1-dB peak signal-to-noise-and-distortion-ratio (SNDR), and 120.3-dB dynamic range (DR) in a 1-kHz bandwidth while consuming 280 μW. This results in a Schreier figure of merit (FoM) of 185.8 dB.

Original languageEnglish
Pages (from-to)1-11
Number of pages11
JournalIEEE Journal of Solid-State Circuits
DOIs
Publication statusE-pub ahead of print - 2018

Keywords

  • A/D conversion
  • asynchronous successive approximation register analog-to-digital converter
  • Bandwidth
  • battery-powered applications
  • Clocks
  • delta-sigma ADC
  • Distance measurement
  • dynamic zoom ADC
  • Energy resolution
  • inverter-based operational transconductance amplifier (OTA)
  • Linearity
  • low-power circuits.
  • Registers
  • Signal resolution

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