A 31-μ W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS

Peng Chen, Feifei Zhang, Zhirui Zong, Suoping Hu, Teerachot Siriburanon, Robert Bogdan Staszewski

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Abstract

This article proposes a power-efficient highly linear capacitor-array-based digital-to-time converter (DTC) using a charge redistribution constant-slope approach. A fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate the starting supply voltage of the constant discharging slope fed to a fixed-threshold comparator. The DTC operation mechanism is analyzed and design tradeoffs are investigated. The proposed DTC consumes merely 31 μW from a 1-V supply when clocked at 40 MHz, while achieving a fine resolution of 148 fs over a 9-bit range. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.96/1.07 LSB.

Original languageEnglish
Article number8850049
Pages (from-to)3075-3085
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume54
Issue number11
DOIs
Publication statusPublished - 1 Nov 2019

Keywords

  • Capacitor-based digital-to-analog converter (C-DAC)
  • constant slope
  • digital-to-time converter (DTC)
  • femtosecond resolution
  • integral nonlinearity (INL)
  • phase-locked loop (PLL)
  • power-efficient
  • ultra-low power (ULP)

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