A 3.2mW SAR-assisted CTΔΣ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS

P. Cenci, M. Bolatkale, R. Rutten, M. Ganzerli, G. Lassche, K. Makinwa, Lucien Breems

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

3 Citations (Scopus)

Abstract

This paper presents a SAR-assisted Continuous-time Delta-Sigma (CT Δ Σ ) ADC, which combines the energy efficiency of SAR ADCs with the relaxed driving requirements of CT Δ Σ ADCs, as well as similar anti-alias filtering. When clocked at 2.4GHz, the ADC achieves 77.5dB SNDR in 40MHz BW. It consumes 3.2mW, resulting in a state-of-the-art Walden FoM of 6.5fJ/cs and a Schreier FOM of 178.5dB.

Original languageEnglish
Title of host publication2019 Symposium on VLSI Circuits
Subtitle of host publicationDigest of technical papers
PublisherIEEE
PagesC230-C231
Number of pages2
ISBN (Electronic)978-4-86348-720-8
ISBN (Print)978-1-7281-0914-5
DOIs
Publication statusPublished - 2019
Event2019 VLSI : Symposium on VLSI Circuits - Kyoto, Japan
Duration: 9 Jun 201914 Jun 2019

Conference

Conference2019 VLSI
CountryJapan
CityKyoto
Period9/06/1914/06/19

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