A 33-GHz LNA for 5G Wireless Systems in 28-nm Bulk CMOS

Mahsa Keshavarz Hedayati, Abdolali Abdipour, Reza Sarraf Shirazi, Cagri Cetintepe, Robert Bogdan Staszewski

Research output: Contribution to journalArticleScientificpeer-review

39 Citations (Scopus)

Abstract

This brief presents a design procedure of a compact 33-GHz low-noise amplifier (LNA) for fifth generation (5G) applications realized in 28-nm LP CMOS. Based on the unique set of challenges presented by advanced nanoscale CMOS, the emphasis is put here on the optimization of design and layout techniques for active and passive components in the presence of rigorous metal density rules and other back-end-of-the-line challenges. All passive components are designed and optimized with full-wave electromagnetic simulations for a high quality factor. In addition, layout techniques help to miniaturize the total area as the suggested 5G frequency band of 33 GHz is not high enough to provide a sufficiently compact chip size. The resulting increase in the concentration of required metal fills furthermore makes this optimization more challenging. The fabricated LNA consists of two cascode stages with a total core area of 0.68 × 0.34 mm2. It exhibits 4.9-dB noise figure and 18.6-dB gain at 33 GHz while consuming only 9.7 mW from a 1.2-V power supply.

Original languageEnglish
Article number8418759
Pages (from-to)1460-1464
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume65
Issue number10
DOIs
Publication statusPublished - 1 Oct 2018
Externally publishedYes

Keywords

  • 28-nm CMOS
  • 5G cellular
  • electromagnetic (EM) modeling
  • Low-noise amplifier (LNA)
  • metal density rules
  • millimeter-wave (mm-wave)
  • system-on-chip (SoC)

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