A 3.5–6.8 GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise

Y. Wu; M. Shahmohammadi; Y. Chen; Ping Lu; R. B. Staszewski

doi:10.1109/ESSCIRC.2016.7598279

A 3.5–6.8 GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise

Y. Wu, M. Shahmohammadi, Y. Chen, Ping Lu, R. B. Staszewski

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

3 Citations (Scopus)

Abstract

We present a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth all-digital PLL (ADPLL). It employs a MASH ΔΣ time-to-digital converter (TDC) to achieve low in-band phase noise, and a wide-tuning range digitally-controlled oscillator (DCO). Fabricated in 40nm CMOS, the ADPLL consumes 10.7 mW while outputting 1.73 to 3.38 GHz (after a ÷2 division) and achieves better than -109 dBc/Hz in-band phase noise and 420fsrms integrated jitter.

Original language	English
Title of host publication	ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference
Publisher	IEEE
Pages	209-212
Number of pages	4
ISBN (Electronic)	978-1-5090-2972-3
ISBN (Print)	978-1-5090-2973-0
DOIs	https://doi.org/10.1109/ESSCIRC.2016.7598279
Publication status	Published - 2016
Event	ESSDERC-ESSCIRC 2016: 42nd European Solid-State Circuits Conference - Lausanne, Switzerland Duration: 12 Sept 2016 → 15 Sept 2016 Conference number: 42 http://esscirc-essderc2016.epfl.ch/

Conference

Conference	ESSDERC-ESSCIRC 2016
Abbreviated title	ESSDERC-ESSCIRC
Country/Territory	Switzerland
City	Lausanne
Period	12/09/16 → 15/09/16
Internet address	http://esscirc-essderc2016.epfl.ch/

Keywords

delta-sigma modulation
digital phase locked loops
integrated circuit noise
jitter
oscillators
phase noise
time-digital conversion
ADPLL
DTC-assisted fractional-N all-digital PLL
MASH ?S TDC
digital-to-time converter
frequency 1.73 GHz to 3.38 GHz
frequency 3.5 GHz to 6.8 GHz
integrated jitter
low-in-band phase noise
power 10.7 mW
size 40 nm
wide-tuning range DCO
wide-tuning range digitally-controlled oscillator
Delays
Frequency measurement
Jitter
Multi-stage noise shaping
Phase locked loops
Phase noise
Tuning
All digital PLL
BBPD
DCO
DTC
MASH
TDC
noise shaping
wide-bandwidth
wide-tuning range

Access to Document

10.1109/ESSCIRC.2016.7598279

Cite this

@inproceedings{74e79b806a13495bab53d26aef221782,

title = "A 3.5–6.8 GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise",

abstract = "We present a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth all-digital PLL (ADPLL). It employs a MASH ΔΣ time-to-digital converter (TDC) to achieve low in-band phase noise, and a wide-tuning range digitally-controlled oscillator (DCO). Fabricated in 40nm CMOS, the ADPLL consumes 10.7 mW while outputting 1.73 to 3.38 GHz (after a ÷2 division) and achieves better than -109 dBc/Hz in-band phase noise and 420fsrms integrated jitter.",

keywords = "delta-sigma modulation, digital phase locked loops, integrated circuit noise, jitter, oscillators, phase noise, time-digital conversion, ADPLL, DTC-assisted fractional-N all-digital PLL, MASH ?S TDC, digital-to-time converter, frequency 1.73 GHz to 3.38 GHz, frequency 3.5 GHz to 6.8 GHz, integrated jitter, low-in-band phase noise, power 10.7 mW, size 40 nm, wide-tuning range DCO, wide-tuning range digitally-controlled oscillator, Delays, Frequency measurement, Jitter, Multi-stage noise shaping, Phase locked loops, Phase noise, Tuning, All digital PLL, BBPD, DCO, DTC, MASH, TDC, noise shaping, wide-bandwidth, wide-tuning range",

author = "Y. Wu and M. Shahmohammadi and Y. Chen and Ping Lu and Staszewski, {R. B.}",

year = "2016",

doi = "10.1109/ESSCIRC.2016.7598279",

language = "English",

isbn = "978-1-5090-2973-0 ",

pages = "209--212",

booktitle = "ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference",

publisher = "IEEE",

address = "United States",

note = "ESSDERC-ESSCIRC 2016 : 42nd European Solid-State Circuits Conference, ESSDERC-ESSCIRC ; Conference date: 12-09-2016 Through 15-09-2016",

url = "http://esscirc-essderc2016.epfl.ch/",

}

Wu, Y, Shahmohammadi, M, Chen, Y, Lu, P & Staszewski, RB 2016, A 3.5–6.8 GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise. in ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference. IEEE, pp. 209-212, ESSDERC-ESSCIRC 2016, Lausanne, Switzerland, 12/09/16. https://doi.org/10.1109/ESSCIRC.2016.7598279

A 3.5–6.8 GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise. / Wu, Y.; Shahmohammadi, M.; Chen, Y. et al.
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference. IEEE, 2016. p. 209-212.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - A 3.5–6.8 GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise

AU - Wu, Y.

AU - Shahmohammadi, M.

AU - Chen, Y.

AU - Lu, Ping

AU - Staszewski, R. B.

N1 - Conference code: 42

PY - 2016

Y1 - 2016

N2 - We present a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth all-digital PLL (ADPLL). It employs a MASH ΔΣ time-to-digital converter (TDC) to achieve low in-band phase noise, and a wide-tuning range digitally-controlled oscillator (DCO). Fabricated in 40nm CMOS, the ADPLL consumes 10.7 mW while outputting 1.73 to 3.38 GHz (after a ÷2 division) and achieves better than -109 dBc/Hz in-band phase noise and 420fsrms integrated jitter.

AB - We present a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth all-digital PLL (ADPLL). It employs a MASH ΔΣ time-to-digital converter (TDC) to achieve low in-band phase noise, and a wide-tuning range digitally-controlled oscillator (DCO). Fabricated in 40nm CMOS, the ADPLL consumes 10.7 mW while outputting 1.73 to 3.38 GHz (after a ÷2 division) and achieves better than -109 dBc/Hz in-band phase noise and 420fsrms integrated jitter.

KW - delta-sigma modulation

KW - digital phase locked loops

KW - integrated circuit noise

KW - jitter

KW - oscillators

KW - phase noise

KW - time-digital conversion

KW - ADPLL

KW - DTC-assisted fractional-N all-digital PLL

KW - MASH ?S TDC

KW - digital-to-time converter

KW - frequency 1.73 GHz to 3.38 GHz

KW - frequency 3.5 GHz to 6.8 GHz

KW - integrated jitter

KW - low-in-band phase noise

KW - power 10.7 mW

KW - size 40 nm

KW - wide-tuning range DCO

KW - wide-tuning range digitally-controlled oscillator

KW - Delays

KW - Frequency measurement

KW - Jitter

KW - Multi-stage noise shaping

KW - Phase locked loops

KW - Phase noise

KW - Tuning

KW - All digital PLL

KW - BBPD

KW - DCO

KW - DTC

KW - MASH

KW - TDC

KW - noise shaping

KW - wide-bandwidth

KW - wide-tuning range

U2 - 10.1109/ESSCIRC.2016.7598279

DO - 10.1109/ESSCIRC.2016.7598279

M3 - Conference contribution

SN - 978-1-5090-2973-0

SP - 209

EP - 212

BT - ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference

PB - IEEE

T2 - ESSDERC-ESSCIRC 2016

Y2 - 12 September 2016 through 15 September 2016

ER -

A 3.5–6.8 GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise

Abstract

Conference

Keywords

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Cite this