A 4 GHz Continuous-Time ΔΣ ADC With 70dB DR and -74dBFS THD in 125MHz BW

Muhammed Bolatkale; Lucien J. Breems; Robert Rutten; Kofi A.A. Makinwa

doi:10.1109/JSSC.2011.2164963

A 4 GHz Continuous-Time ΔΣ ADC With 70dB DR and -74dBFS THD in 125MHz BW

Muhammed Bolatkale, Lucien J. Breems, Robert Rutten, Kofi A.A. Makinwa

Electronic Instrumentation

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Abstract

A 4 GHz third-order continuous-time ΔΣ ADC is presented with a loop filter topology that absorbs the pole caused by the input capacitance of its 4-bit quantizer and also compensates for the excess delay caused by the quantizer's latency. The ADC was implemented in 45 nm-LP CMOS and achieves 70 dB DR and -74 dBFS THD in a 125 MHz BW, while dissipating 260 mW from 1.1/1.8 V supply. The ADC occupies 0.9 mm 2 including the modulator, clock circuitry and decimation filter.

Original language	English
Pages (from-to)	2857-2868
Number of pages	12
Journal	IEEE Journal of Solid State Circuits
Volume	46
Issue number	12
DOIs	https://doi.org/10.1109/JSSC.2011.2164963
Publication status	Published - 2011

Bibliographical note

Accepted Author Manuscript

Keywords

Analog-to-digital conversion
base stations
CMOS analog integrated circuits
continuous-time filters
continuous-time sigma-delta modulation
delta-sigma modulator
multi-bit
oversampling ADCs
radio receivers
wireless communication

Access to Document

10.1109/JSSC.2011.2164963

2095722a - 06029947Accepted author manuscript, 2.01 MB

Cite this

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title = "A 4 GHz Continuous-Time ΔΣ ADC With 70dB DR and -74dBFS THD in 125MHz BW",

abstract = "A 4 GHz third-order continuous-time ΔΣ ADC is presented with a loop filter topology that absorbs the pole caused by the input capacitance of its 4-bit quantizer and also compensates for the excess delay caused by the quantizer's latency. The ADC was implemented in 45 nm-LP CMOS and achieves 70 dB DR and -74 dBFS THD in a 125 MHz BW, while dissipating 260 mW from 1.1/1.8 V supply. The ADC occupies 0.9 mm 2 including the modulator, clock circuitry and decimation filter.",

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AU - Rutten, Robert

AU - Makinwa, Kofi A.A.

N1 - Accepted Author Manuscript

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AB - A 4 GHz third-order continuous-time ΔΣ ADC is presented with a loop filter topology that absorbs the pole caused by the input capacitance of its 4-bit quantizer and also compensates for the excess delay caused by the quantizer's latency. The ADC was implemented in 45 nm-LP CMOS and achieves 70 dB DR and -74 dBFS THD in a 125 MHz BW, while dissipating 260 mW from 1.1/1.8 V supply. The ADC occupies 0.9 mm 2 including the modulator, clock circuitry and decimation filter.

KW - Analog-to-digital conversion

KW - base stations

KW - CMOS analog integrated circuits

KW - continuous-time filters

KW - continuous-time sigma-delta modulation

KW - delta-sigma modulator

KW - multi-bit

KW - oversampling ADCs

KW - radio receivers

KW - wireless communication

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DO - 10.1109/JSSC.2011.2164963

M3 - Article

SN - 0018-9200

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JO - IEEE Journal of Solid State Circuits

JF - IEEE Journal of Solid State Circuits

IS - 12

ER -

A 4 GHz Continuous-Time ΔΣ ADC With 70dB DR and -74dBFS THD in 125MHz BW

Abstract

Bibliographical note

Keywords

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