A 4GHz clock distribution architecture using subharmonically injection-locked coupled oscillators with clock skew calibration in 16nm CMOS

Lan-Chou Cho, Feng-Wei Kuo, Ron Chen, Jack Liu, Chewn-Pu Jou, Fu-Lung Hsueh, R. Bogdan Staszewski

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

1 Citation (Scopus)

Abstract


Original languageEnglish
Title of host publicationDigest of Technical Papers - 2017 Symposium on VLSI Circuits
Place of PublicationPiscataway, NJ
PublisherIEEE
PagesC130-C131
Number of pages2
ISBN (Electronic)978-4-86348-614-0
ISBN (Print)978-4-86348-606-5
DOIs
Publication statusPublished - 2017
Externally publishedYes
Event2017 Symposium on VLSI Technology and Circuits: 2017 VLSI Technology Symposium - 2017 VLSI Circuits Symposium - Kyoto, Japan
Duration: 5 Jun 20178 Jun 2017
http://vlsisymposium.org/2017/

Conference

Conference2017 Symposium on VLSI Technology and Circuits
CountryJapan
CityKyoto
Period5/06/178/06/17
Internet address

Bibliographical note

C10-4

Keywords

  • Clocks
  • Oscillators
  • Calibration
  • Jitter
  • Tuning
  • Delays
  • Pulse generation

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