A 56.4-to-63.4GHz spurious-free all-digital fractional-N PLL in 65nm CMOS

W Wu; X Bai; RB Staszewski; JR Long

doi:10.1109/ISSCC.2013.6487766

A 56.4-to-63.4GHz spurious-free all-digital fractional-N PLL in 65nm CMOS

W Wu, X Bai, RB Staszewski, JR Long

Electronics

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

41 Citations (Scopus)

Original language	English
Title of host publication	2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers
Editors	A Chandrasakan, B Nauta
Place of Publication	Piscataway, NJ, USA
Publisher	IEEE Society
Pages	352-354
Number of pages	3
ISBN (Print)	978-1-4673-4516-3
DOIs	https://doi.org/10.1109/ISSCC.2013.6487766
Publication status	Published - 2013
Event	ISSCC 2013 - San Francisco, CA, United States Duration: 17 Feb 2013 → 21 Feb 2013

Publication series

Name
Publisher	IEEE

Conference

Conference	ISSCC 2013
Country	United States
City	San Francisco, CA
Period	17/02/13 → 21/02/13

Access to Document

10.1109/ISSCC.2013.6487766

Cite this

@inproceedings{561372a594e64a39a7db1c909341eb77,

title = "A 56.4-to-63.4GHz spurious-free all-digital fractional-N PLL in 65nm CMOS",

author = "W Wu and X Bai and RB Staszewski and JR Long",

year = "2013",

doi = "10.1109/ISSCC.2013.6487766",

language = "English",

isbn = "978-1-4673-4516-3",

publisher = "IEEE Society",

pages = "352--354",

editor = "A Chandrasakan and B Nauta",

booktitle = "2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers",

note = "ISSCC 2013 ; Conference date: 17-02-2013 Through 21-02-2013",

}

Wu, W, Bai, X, Staszewski, RB & Long, JR 2013, A 56.4-to-63.4GHz spurious-free all-digital fractional-N PLL in 65nm CMOS. in A Chandrasakan & B Nauta (eds), 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers. IEEE Society, Piscataway, NJ, USA, pp. 352-354, ISSCC 2013, San Francisco, CA, United States, 17/02/13. https://doi.org/10.1109/ISSCC.2013.6487766

A 56.4-to-63.4GHz spurious-free all-digital fractional-N PLL in 65nm CMOS. / Wu, W; Bai, X; Staszewski, RB; Long, JR.

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers. ed. / A Chandrasakan; B Nauta. Piscataway, NJ, USA : IEEE Society, 2013. p. 352-354.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - A 56.4-to-63.4GHz spurious-free all-digital fractional-N PLL in 65nm CMOS

AU - Wu, W

AU - Bai, X

AU - Staszewski, RB

AU - Long, JR

PY - 2013

Y1 - 2013

U2 - 10.1109/ISSCC.2013.6487766

DO - 10.1109/ISSCC.2013.6487766

M3 - Conference contribution

SN - 978-1-4673-4516-3

SP - 352

EP - 354

BT - 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers

A2 - Chandrasakan, A

A2 - Nauta, B

PB - IEEE Society

CY - Piscataway, NJ, USA

T2 - ISSCC 2013

Y2 - 17 February 2013 through 21 February 2013

ER -