A 6.3 μW 20 bit Incremental Zoom-ADC with 6 ppm INL and 1 μV Offset

Youngcheol Chae, Kamran Souri, Kofi A.A. Makinwa

Research output: Contribution to journalArticleScientificpeer-review

78 Citations (Scopus)
81 Downloads (Pure)


A 20-bit incremental ADC for battery-powered sensor applications is presented. It is based on an energy-efficient zoom ADC architecture, which employs a coarse 6-bit SAR conversion followed by a fine 15-bit ΔΣ conversion. To further improve its energy efficiency, the ADC employs integrators based on cascoded dynamic inverters for extra gain and PVT tolerance. Dynamic error correction techniques such as auto-zeroing, chopping and dynamic element matching are used to achieve both low offset and high linearity. Measurements show that the ADC achieves 20-bit resolution, 6 ppm INL and 1 μV offset in a conversion time
of 40 ms, while drawing only 3.5 μA current from a 1.8 V supply. This corresponds to a state-of-the-art figure-of-merit (FoM) of 182.7 dB. The 0.35 mm² chip was fabricated in a standard 0.16 μm CMOS process.
Original languageEnglish
Pages (from-to)3019-3027
Number of pages9
JournalIEEE Journal of Solid State Circuits
Issue number12
Publication statusPublished - 2013


  • A/D conversion
  • and dynamic error correction techniques
  • battery-powered sensors
  • delta-sigma ADC
  • incremental ADC
  • inverter-based integrator
  • low power circuits
  • zoom ADC

Fingerprint Dive into the research topics of 'A 6.3 μW 20 bit Incremental Zoom-ADC with 6 ppm INL and 1 μV Offset'. Together they form a unique fingerprint.

  • Cite this