A 96-channel full data rate direct neural interface in 0.13um CMOS

RM Walker, H. Gao, P Nuyujukian, KAA Makinwa, KV Shenoy, T Meng, B Murmann

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Original languageEnglish
Title of host publicationProceedings Symposium VLSI Circuits Digest of Technical Papers
EditorsM Nagata
Place of PublicationPiscataway, NJ, USA
PublisherIEEE Society
Pages144-145
Number of pages2
ISBN (Print)978-4-86348-165-7
Publication statusPublished - 2011
Event2011 Symposium VLSI Circuits Digest of Technical Papers, Kyoto, Japan - Piscataway, NJ, USA
Duration: 15 Jun 201117 Jun 2011

Publication series

Name
PublisherIEEE

Conference

Conference2011 Symposium VLSI Circuits Digest of Technical Papers, Kyoto, Japan
Period15/06/1117/06/11

Cite this

Walker, RM., Gao, H., Nuyujukian, P., Makinwa, KAA., Shenoy, KV., Meng, T., & Murmann, B. (2011). A 96-channel full data rate direct neural interface in 0.13um CMOS. In M. Nagata (Ed.), Proceedings Symposium VLSI Circuits Digest of Technical Papers (pp. 144-145). IEEE Society.