A 96-channel full data rate direct neural interface in 0.13um CMOS

RM Walker; H. Gao; P Nuyujukian; KAA Makinwa; KV Shenoy; T Meng; B Murmann

A 96-channel full data rate direct neural interface in 0.13um CMOS

RM Walker, H. Gao, P Nuyujukian, KAA Makinwa, KV Shenoy, T Meng, B Murmann

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Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

Original language	English
Title of host publication	Proceedings Symposium VLSI Circuits Digest of Technical Papers
Editors	M Nagata
Place of Publication	Piscataway, NJ, USA
Publisher	IEEE Society
Pages	144-145
Number of pages	2
ISBN (Print)	978-4-86348-165-7
Publication status	Published - 2011
Event	2011 Symposium VLSI Circuits Digest of Technical Papers, Kyoto, Japan - Piscataway, NJ, USA Duration: 15 Jun 2011 → 17 Jun 2011

Publication series

Name
Publisher	IEEE

Conference

Conference	2011 Symposium VLSI Circuits Digest of Technical Papers, Kyoto, Japan
Period	15/06/11 → 17/06/11

Cite this

@inproceedings{12afd295ed03445fb366bccb927ef907,

title = "A 96-channel full data rate direct neural interface in 0.13um CMOS",

author = "RM Walker and H. Gao and P Nuyujukian and KAA Makinwa and KV Shenoy and T Meng and B Murmann",

year = "2011",

language = "English",

isbn = "978-4-86348-165-7",

publisher = "IEEE Society",

pages = "144--145",

editor = "M Nagata",

booktitle = "Proceedings Symposium VLSI Circuits Digest of Technical Papers",

note = "2011 Symposium VLSI Circuits Digest of Technical Papers, Kyoto, Japan ; Conference date: 15-06-2011 Through 17-06-2011",

}

A 96-channel full data rate direct neural interface in 0.13um CMOS. / Walker, RM; Gao, H.; Nuyujukian, P et al.
Proceedings Symposium VLSI Circuits Digest of Technical Papers. ed. / M Nagata. Piscataway, NJ, USA: IEEE Society, 2011. p. 144-145.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - A 96-channel full data rate direct neural interface in 0.13um CMOS

AU - Walker, RM

AU - Gao, H.

AU - Nuyujukian, P

AU - Makinwa, KAA

AU - Shenoy, KV

AU - Meng, T

AU - Murmann, B

PY - 2011

Y1 - 2011

UR - https://npl.stanford.edu/~paul/web/pubs/WalkerEtAlVLSIC2011.pdf

M3 - Conference contribution

SN - 978-4-86348-165-7

SP - 144

EP - 145

BT - Proceedings Symposium VLSI Circuits Digest of Technical Papers

A2 - Nagata, M

PB - IEEE Society

CY - Piscataway, NJ, USA

T2 - 2011 Symposium VLSI Circuits Digest of Technical Papers, Kyoto, Japan

Y2 - 15 June 2011 through 17 June 2011

ER -

A 96-channel full data rate direct neural interface in 0.13um CMOS

Publication series

Conference

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Cite this