Abstract
The cryogenic electronic interface for quantum pro-cessors requires cryo-CMOS embedded memories that cover a wide range of specifications. The temperature dependence of device parameters, such as the threshold voltage, the gate/subthreshold leakage, and the variability, severely alters the memories' performance between room temperature (RT) and cryogenic temperatures (4.2K). To assess the best memory design for a given application, this paper benchmarks three custom DRAMs and a custom SRAM in 40-nm CMOS at 4.2 K and RT, e.g., identifying that, while the SRAM is more power efficient for moderate-to-high speeds at RT, the 2T DRAM performs better than SRAM and 3T DRAMs at 4.2 K.
Original language | English |
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Title of host publication | ESSCIRC 2023 - IEEE 49th European Solid State Circuits Conference |
Publisher | IEEE |
Pages | 165-168 |
Number of pages | 4 |
ISBN (Electronic) | 9798350304206 |
DOIs | |
Publication status | Published - 2023 |
Event | 49th IEEE European Solid State Circuits Conference, ESSCIRC 2023 - Lisbon, Portugal Duration: 11 Sept 2023 → 14 Sept 2023 |
Publication series
Name | European Solid-State Circuits Conference |
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Volume | 2023-September |
ISSN (Print) | 1930-8833 |
Conference
Conference | 49th IEEE European Solid State Circuits Conference, ESSCIRC 2023 |
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Country/Territory | Portugal |
City | Lisbon |
Period | 11/09/23 → 14/09/23 |
Bibliographical note
Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-careOtherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.
Keywords
- Cryo-CMOS
- DRAM
- eDRAM
- SRAM
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Data underlying the publication: A Benchmark of Cryo-CMOS Embedded SRAM/DRAMs in 40-nm CMOS
Damsteegt, R. A. (Creator), TU Delft - 4TU.ResearchData, 9 Apr 2024
DOI: 10.4121/3886EF40-1B1A-479F-A5C4-D3584B90E8A4
Dataset/Software: Dataset