A biasing model for analog circuits based on nullators and norators

E Yildiz; A Sarmiento-Reyes; CJM Verhoeven; A van Staveren

A biasing model for analog circuits based on nullators and norators

E Yildiz, A Sarmiento-Reyes, CJM Verhoeven, A van Staveren

Electronics

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

Original language	Undefined/Unknown
Title of host publication	Proceedings
Editors	H Varwijk
Place of Publication	Utrecht
Publisher	STW Technology Foundation
Pages	743-745
Number of pages	3
ISBN (Print)	90-73461-29-4
Publication status	Published - 2001
Event	ProRISC/IEEE Workshop on Semiconductors, Circuits, Systems and Signal Processing., Veldhoven - Utrecht Duration: 29 Nov 2001 → 30 Nov 2001

Publication series

Name
Publisher	STW technology foundation

Conference

Conference	ProRISC/IEEE Workshop on Semiconductors, Circuits, Systems and Signal Processing., Veldhoven
Period	29/11/01 → 30/11/01

Keywords

ZX Int.klas.verslagjaar < 2002

Cite this

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title = "A biasing model for analog circuits based on nullators and norators",

keywords = "ZX Int.klas.verslagjaar < 2002",

author = "E Yildiz and A Sarmiento-Reyes and CJM Verhoeven and {van Staveren}, A",

year = "2001",

language = "Undefined/Unknown",

isbn = "90-73461-29-4",

publisher = "STW Technology Foundation",

pages = "743--745",

editor = "{H Varwijk}",

booktitle = "Proceedings",

note = "ProRISC/IEEE Workshop on Semiconductors, Circuits, Systems and Signal Processing., Veldhoven ; Conference date: 29-11-2001 Through 30-11-2001",

}

TY - GEN

T1 - A biasing model for analog circuits based on nullators and norators

AU - Yildiz, E

AU - Sarmiento-Reyes, A

AU - Verhoeven, CJM

AU - van Staveren, A

PY - 2001

Y1 - 2001

KW - ZX Int.klas.verslagjaar < 2002

M3 - Conference contribution

SN - 90-73461-29-4

SP - 743

EP - 745

BT - Proceedings

A2 - H Varwijk, null

PB - STW Technology Foundation

CY - Utrecht

T2 - ProRISC/IEEE Workshop on Semiconductors, Circuits, Systems and Signal Processing., Veldhoven

Y2 - 29 November 2001 through 30 November 2001

ER -