A BJT-Based Temperature-to-Digital Converter with ±60 mK (3 σ) Inaccuracy From-55 °c to +125 °c in 0.16-μm CMOS

Bahman Yousefzadeh, Saleh Heidary Shalmany, Kofi A.A. Makinwa

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This paper presents a precision CMOS temperature-to-digital converter (TDC), which senses the temperature-dependent base-emitter voltage of substrate PNPs. Measurements on 20 samples from one batch show that it achieves an inaccuracy of ±60 mK (3σ) from-55 °C to +125 °C, after a single room-temperature trim. This state-of-the-art result is mainly due to the extensive use of dynamic error cancellation techniques to generate the PNP's collector currents, thus minimizing the spread in their base-emitter voltages, together with a digital PTAT trim to correct for the spread in the PNP's saturation currents. The effect of process variation on the TDC's inaccuracy was investigated by measuring 80 samples from three different batches. Using the same calibration parameters, they exhibit a maximum untrimmed inaccuracy of ±2 °C (3σ) from-55 °C to +125 °C. This drops to ±100 mK (3σ) after a single point trim. The proposed TDC thus reduces calibration costs by obviating the need for batch-specific calibration parameters, which would otherwise require the multipoint calibration of several samples. The effect of the PNP's current gain β was also investigated with the help of a novel β-detection circuit. Implemented in 0.16-μm CMOS, the TDC occupies 0.16 mm2 and draws 4.6 μA from 1.5 to 2 V supply voltages. It achieves a resolution Figure of Merit of 7.8 pJ°C2, and a state-of-the-art supply sensitivity of 0.01 °C/V.

Original languageEnglish
Article number7829254
Pages (from-to)1044-1052
Number of pages9
JournalIEEE Journal of Solid State Circuits
Issue number4
Publication statusPublished - 2017

Bibliographical note

Accepted Author Manuscript


  • Batch calibration
  • low-cost calibration
  • proportional to absolute temperature (PTAT) trim
  • substrate PNP
  • temperature sensor
  • temperature-to-digital converter (TDC)


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