A Capacitively Degenerated 100-dB Linear 20-150 MS/s Dynamic Amplifier

Md Shakil Akter*, Kofi A.A. Makinwa, Klaas Bult

*Corresponding author for this work

Research output: Contribution to journalArticleScientificpeer-review

21 Citations (Scopus)
341 Downloads (Pure)


This paper presents a new dynamic residue amplifier topology for pipelined analog-to-digital converters. With an input signal of 100 mVpp,diff and 4 × gain, it achieves-100-dB total harmonic distortion, the lowest ever reported for a dynamic amplifier. Compared to the state of the art, it exhibits 25 dB better linearity with twice the output swing and similar noise performance. The key to this performance is a new linearization technique based on capacitive degeneration, which exploits the exponential voltage-to-current relationship of MOSFET in weak inversion. The prototype amplifier is fabricated in a 28-nm CMOS process and dissipates only 87 μW at a clock speed of 43 MS/s, thereby improving the energy per cycle by 26 × compared with that of state-of-the-art high-linearity amplifiers.

Original languageEnglish
Pages (from-to)1115-1126
Number of pages12
JournalIEEE Journal of Solid State Circuits
Issue number4
Publication statusPublished - 2018

Bibliographical note

Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care
Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.


  • Amplifier
  • analog linearization technique
  • analog-to-digital converter (ADC)
  • capacitive degeneration
  • cross-coupled capacitors
  • digital nonlinearity calibration
  • dynamic residue amplifier
  • integrator
  • split-capacitor technique


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