A Capacitively-Degenerated 100dB Linear 20-150MS/s Dynamic Amplifier

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Abstract

This paper presents a new dynamic residue amplifier for pipelined ADCs. With an input of 100mVpp,diff and 4x gain, it achieves -100dB THD, the lowest ever reported in dynamic amplifiers. Compared to the state-of-the-art, it exhibits >25dB better linearity with >2x larger output swing and similar noise performance. The key to this is a new linearization technique based on capacitive-degeneration. Fabricated in a 28nm CMOS, the prototype amplifier dissipates 87μW at a clock speed of 43MS/s and maintains -100dB THD up to 150MS/s.
Original languageEnglish
Title of host publicationDigest of Technical Papers - 2017 Symposium on VLSI Circuits
Place of PublicationPiscataway, NJ
PublisherIEEE
PagesC136-C137
Number of pages2
ISBN (Electronic)978-4-86348-614-0
ISBN (Print)978-4-86348-606-5
DOIs
Publication statusPublished - 2017
Event2017 Symposium on VLSI Technology and Circuits: 2017 VLSI Technology Symposium - 2017 VLSI Circuits Symposium - Kyoto, Japan
Duration: 5 Jun 20178 Jun 2017
http://vlsisymposium.org/2017/

Conference

Conference2017 Symposium on VLSI Technology and Circuits
CountryJapan
CityKyoto
Period5/06/178/06/17
Internet address

Keywords

  • Capacitors
  • Linearity
  • Gain
  • Clocks
  • Calibration
  • Harmonic analysis
  • Current measurement

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