Abstract
This paper presents a new dynamic residue amplifier for pipelined ADCs. With an input of 100mVpp,diff and 4x gain, it achieves -100dB THD, the lowest ever reported in dynamic amplifiers. Compared to the state-of-the-art, it exhibits >25dB
better linearity with >2x larger output swing and similar noise performance. The key to this is a new linearization technique based on capacitive-degeneration. Fabricated in a 28nm CMOS, the prototype amplifier dissipates 87μW at a clock
speed of 43MS/s and maintains -100dB THD up to 150MS/s.
| Original language | English |
|---|---|
| Title of host publication | Digest of Technical Papers - 2017 Symposium on VLSI Circuits |
| Place of Publication | Piscataway, NJ |
| Publisher | IEEE |
| Pages | C136-C137 |
| Number of pages | 2 |
| ISBN (Electronic) | 978-4-86348-614-0 |
| ISBN (Print) | 978-4-86348-606-5 |
| DOIs | |
| Publication status | Published - 2017 |
| Event | 2017 Symposium on VLSI Technology and Circuits: 2017 VLSI Technology Symposium - 2017 VLSI Circuits Symposium - Kyoto, Japan Duration: 5 Jun 2017 → 8 Jun 2017 http://vlsisymposium.org/2017/ |
Conference
| Conference | 2017 Symposium on VLSI Technology and Circuits |
|---|---|
| Country/Territory | Japan |
| City | Kyoto |
| Period | 5/06/17 → 8/06/17 |
| Internet address |
Bibliographical note
C11-1Keywords
- Capacitors
- Linearity
- Gain
- Clocks
- Calibration
- Harmonic analysis
- Current measurement