A Chip-Package Multi-Level Coupled Electro-Thermo-Mechanical Modeling for SiC MOSFETs and Package-Level Avalanche Ruggedness Enhancement

Silicon Carbide (SiC) MOSFETs face critical challenges in avalanche ruggedness under repetitive low-energy stresses, yet the underlying failure mechanisms and reinforcement strategies remain underexplored. This study investigates the degradation of a 1200 V/40 mΩ planar-gate SiC MOSFET through stepped single-pulse and multi-pulse unclamped inductive switching (UIS) tests. Experimental results demonstrate a 20.18 mΩ increase in on-resistance (Rdson) after 30,000 repetitive avalanche cycles, attributed primarily to bond wire aging and solder delamination. A chip-package multi-level coupled electro-thermo-mechanical model is developed, bridging carrier dynamics and package-level electro-thermo-mechanical coupled stress. The calibrated model reproduces the electrical characteristics and transient thermal response (<1.5% error) of the real device. Simulations highlight that localized electric fields exceeding 15 MV/m at bond pads and cyclic thermo-mechanical strain accelerate package-level degradation. Guided by these findings, two reinforcement strategies—increased bond-pad contact area and higher wire count—are proposed. Experimental validation over 50,000 UIS cycles demonstrates reductions in R_dson degradation of 30.1% and 36.4%, respectively, prolonging predicted fatigue life from 16,000 to 24,000 cycles. The combined experimental–simulation framework offers a scalable design methodology for extending the avalanche safe operating area of SiC MOSFETs without compromising static performance.